参数资料
型号: AGLE600V5-FG256C
元件分类: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA256
封装: 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256
文件页数: 135/156页
文件大小: 5023K
代理商: AGLE600V5-FG256C
IGLOOe Device Family Overview
1- 4
v1.2
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)
programming of IGLOOe devices via an IEEE 1532 JTAG interface.
Flash*Freeze Technology
The IGLOOe device has an ultra-low power static mode, called Flash*Freeze mode, which retains all
SRAM and register information and can still quickly return to normal operation. Flash*Freeze
technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating
the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and
global I/Os can still be driven and can be toggling without impact on power consumption, clocks
can still be driven or can be toggling without impact on power consumption, and the device retains
all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode
or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No
power is consumed by the I/O banks, clocks, JTAG pins, or PLL in this mode.
Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the
power management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to
decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a
regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the
Figure 1-1 IGLOOe Device Architecture Overview
4,608-Bit Dual-Port SRAM
or FIFO Block
VersaTile
RAM Block
CCC
Pro I/Os
4,608-Bit Dual-Port SRAM
or FIFO Block
RAM Block
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
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AGLE600V5-FG484C FPGA, 13824 CLBS, 600000 GATES, PBGA484
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相关代理商/技术参数
参数描述
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