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参数资料
型号： AGLE600V5-FGG484C
元件分类： FPGA
英文描述： FPGA, 13824 CLBS, 600000 GATES, PBGA484
封装： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484
文件页数： 31/156页
文件大小： 5023K
代理商： AGLE600V5-FGG484C
IGLOOe DC and Switching Characteristics
2- 112
Advance v0.3
Advance v0.1
(continued)
Table 2-13 Summary of I/O Output Buffer Power (per pin) – Default I/O
Software Settings1 was updated to change PDC3 to PDC7. The table notes were
updated to reflect that power was measured on VCCI. Table note 4 is new.
2-10
Table 2-15 Different
Components
Contributing
to
the
Static
Power
Consumption in IGLOO Devices and Table 2-17 Different Components
Contributing to the Static Power Consumption in IGLOO Devices were
updated to add PDC6 and PDC7, and to change the definition for PDC5 to bank
quiescent power.
2-11,
2-12
A
table
subtitle
was
added
for
Table 2-17 Different
Components
Contributing to the Static Power Consumption in IGLOO Devices
2-12
The "Total Static Power Consumption—PSTAT" section was updated to revise
the calculation of PSTAT, including PDC6 and PDC7.
2-13
Footnote 1 was updated to include information about PAC13. The PLL
Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to PPLL
= PDC4 + PAC13 * FCLKOUT.
2-14
The "Timing Model" was updated to be consistent with the revised timing
numbers.
2-16
In Table 2-21 Summary of Maximum and Minimum DC Input Levels, TJ was
changed to TA in notes 1 and 2.
2-21
Table 2-31 Schmitt Trigger Input Hysteresis was updated to included a
hysteresis value for 1.2 V LVCMOS (Schmitt trigger mode).
2-28
All AC Loading figures for single-ended I/O standards were changed from
Datapaths at 35 pF to 5 pF.
N/A
The "1.2 V LVCMOS (JESD8-12A)" section is new.
2-41
Advance v0.4
(December 2007)
This document was previously in datasheet Advance v0.4. As a result of
moving to the handbook format, Actel has restarted the version numbers. The
new version number is Advance v0.1.
N/A
Advance v0.3
(September 2007)
Table 2-4 IGLOOe CCC/PLL Specification and Table 2-5 IGLOOe CCC/PLL
Specification were updated.
2-18,
2-19
The "During Flash*Freeze Mode" section was updated to include information
about the output of the I/O to the FPGA core
.
2-60
Figure 2-38 Flash*Freeze Mode Type 1 – Timing Diagram was updated to
modify the LSICC signal.
2-56
Table 2-32 Flash*Freeze Pin Location in IGLOOe Family Packages (device-
independent) was updated for the FG896 package.
2-64
Figure 2-40 Flash*Freeze Mode Type 2 – Timing Diagram was updated to
modify the LSICC Signal.
2-58
Information regarding calculation of the quiescent supply current was added
to the "Quiescent Supply Current" section.
3-6
Table 3-8 Quiescent Supply Current (IDD), IGLOOe Flash*Freeze Mode was
updated.
3-6
Table 3-9 Quiescent Supply Current (IDD), IGLOOe Sleep Mode (VCC = 0 V)
was updated.
3-6
Table 3-11 Quiescent Supply Current, No IGLOOe Flash*Freeze Mode1 was
updated.
3-6
Previous Version
Changes in Current Version (Advance v0.3)
Page
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相关代理商/技术参数
参数描述
AGLE600V5-FGG484I 功能描述:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOOe 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23）
AGLE600V5-FGG896 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FGG896ES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FGG896I 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FGG896PP 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
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