参数资料
| 型号： | AGLN125V2-CSG81 |
| 厂商： | Microsemi SoC |
| 文件页数： | 53/150页 |
| 文件大小： | 0K |
| 描述： | IC FPGA NANO 1KB 125K 81-CSP |
| 标准包装： | 640 |
| 系列： | IGLOO nano |
| 逻辑元件/单元数： | 3072 |
| RAM 位总计： | 36864 |
| 输入/输出数： | 60 |
| 门数： | 125000 |
| 电源电压： | 1.14 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -20°C ~ 70°C |
| 封装/外壳： | 81-WFBGA，CSBGA |
| 供应商设备封装： | 81-CSP（5x5） |
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Datasheet Information
5-6
Revision 17
Revision 2 (Dec 2008)
Product Brief Advance
v0.4
The second table note in "IGLOO nano Devices" table was revised to state,
"AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.
AGLN030 and smaller devices do not support this feature."
The I/Os per package for CS81 were revised to 60 for AGLN060, AGLN125, and
AGLN250 in the "I/Os Per Package"table.
Packaging Advance
v0.3
The "UC36" pin table is new.
Revision 1 (Nov 2008)
Product Brief Advance
v0.3
The "Advanced I/Os" section was updated to include wide power supply voltage
support for 1.14 V to 1.575 V.
The AGLN030 device was added to product tables and replaces AGL030 entries
that were formerly in the tables.
The "I/Os Per Package"table was updated for the CS81 package to change the
number of I/Os for AGLN060, AGLN125, and AGLN250 from 66 to 64.
The "Wide Range I/O Support" section is new.
The table notes and references were revised in Table 2-2 Recommended
Operating Conditions 1. VMV was included with VCCI and a table note was added
stating, "VMV pins must be connected to the corresponding VCCI pins. See Pin
Descriptions for further information." Please review carefully.
VJTAG was added to the list in the table note for Table 2-9 Quiescent Supply
added for AGLN010, AGLN015, and AGLN030 for 1.5 V.
VCCI was removed from the list in the table note for Table 2-10 Quiescent
Values for ICCA current were updated for AGLN010, AGLN015, and AGLN030 in
Values for PAC1 and PAC2 were added to Table 2-15 Different Components
Table notes regarding wide range support were added to Table 2-21 Summary of
1.2 V LVCMOS wide range values were added to Table 2-22 Summary of
The following table note was added to Table 2-25 Summary of I/O Timing
Timing Characteristics—Software Default Settings: "All LVCMOS 3.3 V software
macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B
specification."
3.3 V LVCMOS Wide Range and 1.2 V Wide Range were added to Table 2-28
Revision / Version
Changes
Page
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AGLN125V2-CSG81I | 功能描述:IC FPGA NANO 1KB 125K 81-CSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| AGLN125V2-CSG81Y | 制造商:Microsemi Corporation 功能描述:Res Thick Film NET 2K Ohm 5% 7/20W ±300ppm/°C ISOL Ceramic 14-Pin Flat Flat SMD Tube |
| AGLN125V2-DIELOT | 制造商:Microsemi Corporation 功能描述:AGLN125V2-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film |
| AGLN125V2-QNG100 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOO NANO 125K GATES COMM 130NM 1.2V/1.5V 100QFN - Trays |
| AGLN125V2-QNG100I | 制造商:Microsemi Corporation 功能描述:FPGA IGLOO NANO 125K GATES IND 130NM 1.2V/1.5V 100QFN - Trays |
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