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参数资料
| 型号： | AM29DS163DB100WAKN |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory |
| 中文描述： | 16兆位的CMOS 1.8伏只，同时作业快闪记忆体 |
| 文件页数： | 30/50页 |
| 文件大小： | 1682K |
| 代理商： | AM29DS163DB100WAKN |
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Am29DS163D
A D V A N C E I N F O R M A T I O N
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is ac-
tively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and
mode information. Refer to
Table 15 on page 31
to
compare outputs for DQ2 and DQ6.
Figure 6, on page 29
shows the toggle bit algorithm in
flowchart form, and the section “DQ2: Toggle Bit II” ex-
plains the algorithm. See also the
“DQ6: Toggle Bit I”
on page 29
subsection.
Figure 22, on page 43
shows
the toggle bit timing diagram.
Figure 23, on page 43
shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 6, on page 29
for the following discus-
sion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of
the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the de-
vice completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device successfully completed the pro-
gram or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the
system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 did not
go high. The system may continue to monitor the tog-
gle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of
Figure 6, on
page 29
).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time ex-
ceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.”
Only an erase operation can
change a “0” back to a “1.”
Under this condition, the
device halts the operation, and when the timing limit is
exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to reading array data (or
to the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure started. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 μs, the system need not
monitor DQ3. See also
“Sector Erase Command Se-
quence” on page 25
.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device accepted the
command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm started; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is “0,” the de-
vice accepts additional sector erase commands. To
ensure the command is accepted, the system software
should check the status of DQ3 prior to and following
each subsequent sector erase command. If DQ3 is
high on the second status check, the last command
might not have been accepted.
Table 15 on page 31
shows the status of DQ3 relative
to the other status bits.
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