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参数资料
型号： AM29F017D-150F4E
厂商： SPANSION LLC
元件分类： DRAM
英文描述： 16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
中文描述： 2M X 8 FLASH 5V PROM, 150 ns, PDSO40
封装： MO-142CD, TSOP-40
文件页数： 4/44页
文件大小： 1021K
代理商： AM29F017D-150F4E
Am29F017D
3
TABLE OF CONTENTS
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29F017D Device Bus Operations.................................. 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status ...................................... 9
Standby Mode ........................................................................ 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode.............................................................. 10
Table 2. Sector Address Table........................................................ 11
Autoselect Mode..................................................................... 12
Table 3. Am29F017D Autoselect Codes (High Voltage Method).... 12
Sector Group Protection/Unprotection.................................... 12
Table 4. Sector Group Addresses................................................... 12
Temporary Sector Group Unprotect ....................................... 12
Figure 1. Temporary Sector Group Unprotect Operation................ 13
Hardware Data Protection...................................................... 13
Low V
CC
Write Inhibit...................................................................... 13
Write Pulse “Glitch” Protection........................................................ 13
Logical Inhibit.................................................................................. 13
Power-Up Write Inhibit.................................................................... 13
Common Flash Memory Interface (CFI). . . . . . . 14
Table 5. CFI Query Identification String.......................................... 14
Table 6. System Interface String..................................................... 14
Table 7. Device Geometry Definition .............................................. 15
Table 8. Primary Vendor-Specific Extended Query ........................ 15
Command Definitions . . . . . . . . . . . . . . . . . . . . . 16
Reading Array Data................................................................ 16
Reset Command..................................................................... 16
Autoselect Command Sequence............................................ 16
Byte Program Command Sequence....................................... 16
Unlock Bypass Command Sequence.............................................. 17
Figure 2. Program Operation .......................................................... 17
Chip Erase Command Sequence........................................... 17
Sector Erase Command Sequence........................................ 18
Erase Suspend/Erase Resume Commands........................... 18
Figure 3. Erase Operation............................................................... 19
Command Definitions............................................................. 20
Table 9. Am29F017D Command Definitions................................... 20
Write Operation Status . . . . . . . . . . . . . . . . . . . . 21
DQ7: Data# Polling................................................................. 21
Figure 4. Data# Polling Algorithm ................................................... 21
RY/BY#: Ready/Busy# ........................................................... 22
DQ6: Toggle Bit I.................................................................... 22
DQ2: Toggle Bit II................................................................... 22
Reading Toggle Bits DQ6/DQ2 .............................................. 22
DQ5: Exceeded Timing Limits................................................ 23
DQ3: Sector Erase Timer ....................................................... 23
Figure 5. Toggle Bit Algorithm........................................................ 23
Table 10. Write Operation Status................................................... 24
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 25
Figure 6. Maximum Negative Overshoot Waveform...................... 25
Figure 7. Maximum Positive Overshoot Waveform........................ 25
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
TTL/NMOS Compatible .......................................................... 26
CMOS Compatible.................................................................. 26
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Test Setup...................................................................... 27
Table 11. Test Specifications......................................................... 27
Key to Switching Waveforms. . . . . . . . . . . . . . . . 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Read-only Operations............................................................. 28
Figure 9. Read Operation Timings................................................. 28
Hardware Reset (RESET#) .................................................... 29
Figure 10. RESET# Timings .......................................................... 29
Erase/Program Operations..................................................... 30
Figure 11. Program Operation Timings.......................................... 31
Figure 12. Chip/Sector Erase Operation Timings .......................... 32
Figure 13. Data# Polling Timings (During Embedded Algorithms). 33
Figure 14. Toggle Bit Timings (During Embedded Algorithms)...... 33
Figure 15. DQ2 vs. DQ6................................................................. 34
Temporary Sector Unprotect .................................................. 34
Figure 16. Temporary Sector Group Unprotect Timing Diagram... 34
Erase and Program Operations.............................................. 35
Alternate CE# Controlled Writes.................................................... 35
Figure 17. Alternate CE# Controlled Write Operation Timings ...... 36
Erase and Programming Performance . . . . . . . . 37
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 37
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 37
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38
TS 040—40-Pin Standard Thin Small Outline Package......... 38
TSR040—40-Pin Reverse Thin Small Outline Package......... 39
TS 048—48-Pin Standard Thin Small Outline Package......... 40
TSR048—48-Pin Reverse Thin Small Outline Package......... 41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision A (July 1997)............................................................ 42
Revision B (January 1998) ..................................................... 42
Revision B+1 (January 1998)................................................. 42
Revision B+2 (April 1998)....................................................... 42
Revision B+3 (August 1998)................................................... 42
Revision C (January 1999)..................................................... 42
Revision C+1 (March 23, 1999).............................................. 42
Revision C+2 (May 17, 1999)................................................. 42
Revision D (November 16, 1999) ........................................... 42
Revision E (May 19, 2000) ..................................................... 43
Revision E+1 (December 5, 2000) ......................................... 43
Revision E+2 (March 23, 2001).............................................. 43
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