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参数资料
| 型号： | Am29F400BT-90SIB |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 4兆位（512亩x 8-Bit/256亩x 16位），5.0伏的CMOS只引导扇区闪存 |
| 文件页数： | 2/37页 |
| 文件大小： | 238K |
| 代理商： | AM29F400BT-90SIB |
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Am29F400B
P R E L IM IN A R Y
GENERAL DESCRIPTION
The Am29F400B is a 4 Mbit, 5.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 44-pin SO and 48-pin TSOP
packages. The word-wide data (x16) appears on
DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
DQ0. This device is designed to be programmed in-
system with the standard system 5.0 volt V
CC
supply.
A 12.0 V V
PP
is not required for write or erase opera-
tions. The device can also be programmed in standard
EPROM programmers.
This device is manufactured using AMD’s 0.35 μm
process technology, and offers all the features and ben-
efits of the Am29F400, which was manufactured using
0.5 μm process technology.
The standard device offers access times of 55, 60, 70,
90, 120, and 150 ns, allowing high speed microproces-
sors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard
. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and
DQ6/DQ2 (toggle)
status bits
. After a program or
erase cycle has been completed, the device is ready to
read array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby mode
.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
相关PDF资料 |
PDF描述 |
|---|---|
| AM29F400BT-90SC0 | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F400BT-90EC | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F400BT-90EC0 | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F400BT-90ED | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F400BT-90ED0 | 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29F800BB-120DPC1 | 制造商:Spansion 功能描述:5V 8M FLASH KNOWN GOOD DIE W/BOTTOM BOOT (COMMERCIAL TEMP) - Gel-pak, waffle pack, wafer, diced wafer on film |
| AM29F800BB120SC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F800BB-55EC | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 8Mbit 1M/512K x 8bit/16bit 55ns 48-Pin TSOP |
| AM29F800BB-55EF | 功能描述:闪存 8M (1MX8/512KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AM29F800BB-55EF\\T | 制造商:Spansion 功能描述:IC 8MEG(512K16)BOTTOM SCTOR 100K (CS39S) |
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