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参数资料
| 型号： | AM29F800BT-55SF |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:55ns; Series:AM29 RoHS Compliant: Yes |
| 中文描述： | 512K X 16 FLASH 5V PROM, 55 ns, PDSO44 |
| 封装： | LEAD FREE, MO-180AA, SOP-44 |
| 文件页数： | 34/45页 |
| 文件大小： | 1382K |
| 代理商： | AM29F800BT-55SF |
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Am29F800B
21504E8 November 17, 2009
D A TA SH EE T
GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 44-pin SO, 48-pin
TSOP, and 48-ball FBGA packages. The device is also
available in Known Good Die (KGD) form. For more
information, refer to publication number 21631. The
word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. This device
is designed to be programmed in-system with the stan-
dard system 5.0 volt VCC supply. A 12.0 V VPP is not
required for write or erase operations. The device can
also be programmed in standard EPROM program-
mers.
This device is manufactured using AMD’s 0.32 m
process technology, and offers all the features and ben-
efits of the Am29F800, which was manufactured using
0.5 m process technology.
The standard device offers access times of 55 and
70 ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
相关PDF资料 |
PDF描述 |
|---|---|
| AM29F800BT-70EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| AM29F800T-120SI | FLASH 5V PROM, PDSO44 |
| AM29LV001BB-70ED | Flash Memory IC; Memory Size:1Mbit; Package/Case:48-TSOP; Supply Voltage Max:3V; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Access Time, Tacc:70nS; Series:AM29 RoHS Compliant: Yes |
| AM29LV002BB-120ED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV002BT-70EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29F800BT-55SI | 制造商:Spansion 功能描述:FLASH PARALLEL 5V 8MBIT 1MX8/512KX16 55NS 44SOIC - Rail/Tube |
| AM29F800BT70EC | 制造商:AMD 功能描述:NEW |
| AM29F800BT-70EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F800BT-70ED | 制造商:Spansion 功能描述:IC SM FLASH 5V 8MB |
| AM29F800BT-70ED | 制造商:Spansion 功能描述:FLASH MEMORY IC |
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