- 您现在的位置：买卖IC网 > PDF目录166216 > AM29PDL127H85PCIN (Spansion Inc.) 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control PDF资料下载
参数资料
| 型号： | AM29PDL127H85PCIN |
| 厂商： | Spansion Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | 128兆位（8米× 16位），3.0伏的CMOS只，页面模式同步读/写闪存与增强VersatileIO控制记忆 |
| 文件页数： | 7/68页 |
| 文件大小： | 750K |
| 代理商： | AM29PDL127H85PCIN |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
June 30, 2003
Am29PDL127H
13
ADV ANCE
I N FO RMAT I O N
(Note that this is a more restricted voltage range than
V
IH.) If CE# and RESET# are held at VIH, but not within
V
IO ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device re-
quires standard access time (t
CE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until th e
operation is completed.
CC3 in the DC Characteristics table represents the
CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC +
150 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Note that during automatic sleep mode, OE# must be
at V
IH before the device reduces current to the stated
sleep mode specification. I
CC5 in the DC Characteris-
tics table represents the automatic sleep mode current
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS±0.3 V, the device
draws CMOS standby current (I
CC4). If RESET# is held
at V
IL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY (during Embedded Algorithms). The
system can th us monito r RY/BY# to de termin e
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
READY (not during Embedded
Algorithms). The system can read data t
RH after the
RESET# pin returns to V
IH.
Refer to the AC Characteristic tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH, output from the device is
disabled. The output pins (except for RY/BY#) are
placed in the highest Impedance state
相关PDF资料 |
PDF描述 |
|---|---|
| AM29PDL127H85VKI | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| AM29PDL127H85VKIN | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| Am29PDL127H88 | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| AM29PDL127H83VKI | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| AM29SL800CB-100ED | 512K X 16 FLASH 1.8V PROM, 100 ns, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29PDL128G70RPEI | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16/4M X 32 70NS 80FBGA - Trays |
| AM29PDL128G80PEF | 制造商:Spansion 功能描述:SPZAM29PDL128G80PEF 128M FLASH EOL100409 |
| AM29PL141BXA | 制造商:AMD 功能描述:* |
| AM29PL141DC | 制造商:Advanced Micro Devices 功能描述:USER PROGRAMMABLE SPECIAL FUNCTION ASIC, 28 Pin, DIP |
| AM29PL160CB-90SF | 制造商:Advanced Micro Devices 功能描述: |
发布紧急采购，3分钟左右您将得到回复。