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| 型号： | AN-53 |
| 厂商： | Fairchild Semiconductor Corporation |
| 元件分类： | DC/DC变换器 |
| 英文描述： | Implementing an RC5051 DC-DC Converter on Pentium II Motherboards |
| 中文描述： | 推行RC5051的DC - DC转换器的奔腾II主板 |
| 文件页数： | 15/20页 |
| 文件大小： | 143K |
| 代理商： | AN-53 |
AN53
APPLICATION NOTE
15
Figure 14. Placement of the MOSFETs
PCB Layout Guidelines and
Considerations
PCB Layout Guidelines
Placement of the MOSFETs relative to the RC5051 is
critical. Place the MOSFETs (Q1 & Q2) so that the trace
length from the RC5051 HIDRV and LODRV pins to the
FET gates is minimized. A long lead length on this pin
would cause high amounts of ringing due to the
inductance of the trace and the large gate capacitance of
the FET. This noise radiates all throughout the board, and,
because it is switching at such a high voltage and
frequency, it is very difficult to suppress.
Figure 14 shows an example of good placement for the
MOSFETs in relation to the RC5051. In addition, this
figure shows an example of problematic placement for the
MOSFETs.
In general, all of the noisy switching lines should be kept
away from the quiet analog section of the RC5051. That is,
traces that connect to pins 9, 12 and 13 (LODRV, HIDRV
and VCCQP) should be kept far away from the traces that
connect to pins 1, 2, 4 and 5, and pin 16.
Place the 0.1
m
F decoupling capacitors as close to the
RC5051 pins as possible. Extra lead length degrades their
ability to suppress noise.
Each VCC and GND pin should have its own via to the
appropriate plane. This helps to provide isolation between
pins.
Surround the CEXT timing capacitor with a ground trace.
Be sure to place a ground or power plane under the
capacitor for further noise isolation to provide additional
shielding to the oscillator pin 1 from the noise on the PCB.
In addition, place this capacitor as close to the RC5051
pin 1 as possible.
Place the MOSFETs, inductor and Schottky as close
together as possible for the same reasons as on the first
bullet above. Place the input bulk capacitors as close to the
drains of MOSFETs as possible. In addition, placement of
a 0.1
m
F decoupling capacitor right on the drain of each
MOSFET helps to suppress some of the high frequency
switching noise on the input of the DC-DC converter.
Place the output bulk capacitors as close to the CPU as
possible to optimize their ability to supply instantaneous
current to the load in the event of a current transient.
Additional space between the output capacitors and the
CPU allows the parasitic resistance of the board traces to
degrade the DC-DC converter’s performance under load
transient conditions, causing higher voltage deviation. For
more detailed information regarding capacitor placement,
refer to Application Bulletin AB-5.
The traces that run from the RC5051 IFB (pin 4) and VFB
(pin 5) pins should be run next to each other and Kelvin
connected to the sense resistor. Running these lines
together prevents some of the common mode noise that is
presented to the RC5051 feedback input. Try, as much as
possible, to run the noisy switching signals (LODRV,
HIDRV & VCCQP) on one layer, but use the inner layers
for power and ground only. If the top layer is being used to
route all of the noisy switching signals, use the bottom
layer to route the analog sensing signals VFB and IFB.
Good layout
8
7
6
2
11
15
14
13
12
3
16
1
5
4
Problem layout
RC505
“Quiet" Pins
=
9
10
17
18
19
20
Q2
Q1
Q1
Q2
65-AP53-08
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