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| 型号： | AN-53 |
| 厂商： | Fairchild Semiconductor Corporation |
| 元件分类： | DC/DC变换器 |
| 英文描述： | Implementing an RC5051 DC-DC Converter on Pentium II Motherboards |
| 中文描述： | 推行RC5051的DC - DC转换器的奔腾II主板 |
| 文件页数： | 2/20页 |
| 文件大小： | 143K |
| 代理商： | AN-53 |
AN53
APPLICATION NOTE
2
Table 2. Intel Pentium II
Processor Power Specifications
NOTES:
1. Maximum power values are measured at typical V
CCP
to take into account the thermal time constant of the CPU package.
2. Flexible motherboard specifications are recommendations only. Actual specifications are subject to change.
CPU Model, Features
Klamath
233MHz
266MHz
300MHz
Deschutes
266MHz
300MHz
333MHz
350MHz
400MHz
450MHz
500MHz
Deschutes Flexible Motherboard
Voltage Specification,
V
CC CORE
(VDC)
2.8V +100mV/-60mV
Maximum Current,
I
CC CORE
(A)
11.8
12.7
14.2
2.0V +100mV/-60mV
2.0V +100mV/-60mV
2.0V +100mV/-60mV
2.0V +/-60mV
2.0V +/-60mV
2.0V +/-60mV
2.0V +/-60mV
2.0V +/-60mV
8.5
9.6
10.6
11.1
12.1
14.2
16.0
18.9
Output Ripple and Noise
Ripple and noise are defined as periodic or random signals
over the frequency band of 0–20MHz at the output pins.
Output ripple and noise must be consistent with voltage
requirements throughout the full load range and under all
specified input voltage conditions.
Efficiency
The efficiency of the DC-DC converter must be greater than
80% at maximum output current and greater than 40% at low
current draw.
Processor Voltage Identification
There are five Voltage Identification Pins, VID4-VID0, on the
Pentium II processor package which can be used to support
automatic selection of the power supply voltage. These pins are
internally unconnected or are shorted to ground (V
SS
). The
logic status of the VID pins defines the voltage required by the
processor. In order to address future low voltage microproces-
sors, the RC5051 includes a VID4 input bit to extend the output
voltage range as low as 1.3V. The output voltage programming
codes are presented in Table 3. A ‘1’ refers to an open pin and a
‘0’ refers to a short to ground.
Note:
1. 0 = processor pin is tied to GND
1 = processor pin is open.
Table 3. Output Voltage Programming
Codes
VID4
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
VID2
1
1
1
1
0
0
0
VID1
1
1
0
0
1
1
0
VID0
1
0
1
0
1
0
1
V
OUT
to CPU
1.30V
1.35V
1.40V
1.45V
1.50V
1.55V
1.60V
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.65V
1.70V
1.75V
1.80V
1.85V
1.90V
1.95V
2.00V
2.05V
No CPU
2.1V
2.2V
2.3V
2.4V
2.5V
2.6V
2.7V
2.8V
2.9V
3.0V
3.1V
3.2V
3.3V
3.4V
3.5V
Table 3. Output Voltage Programming
Codes
(continued)
VID4
VID3
VID2
VID1
VID0
V
OUT
to CPU
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