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参数资料
| 型号： | AN1504D |
| 厂商： | ON SEMICONDUCTOR |
| 英文描述： | Metastability and the ECLinPS Family |
| 中文描述： | 亚稳态和业界的EClinPS家庭 |
| 文件页数： | 4/8页 |
| 文件大小： | 135K |
| 代理商： | AN1504D |
AN1504/D
http://onsemi.com
4
Metastable Equations
Flip
flop propagation delay as a function of the input
signal is represented in Figure 6.
T
D
T
P
T
MAX
T
0
T
F
DATA
INPUT
TIME
Figure 6. Flip
Flop Response Time Plot
P
t
T
W
(T
D
)
The ordinate is the flip
flop propagation delay time, and
the abscissa is the time that data arrives at the flip
flop input
relative to reference time, T
0
. For devices with positive
set
up times T
0
represents the clock transition time with the
difference between T
0
and T
MAX
being the minimum
allowable set
up time. Thus data arriving before time T
MAX
will elicit a nominal propagation delay, T
P
, when clocked.
For data appearing between times T
MAX
and T
F
the
propagation delay will be longer than T
P
because the set
up
and/or hold times have been violated; and the device enters
the metastable state. Data occurring at the input after time T
F
will have no affect on the output, hence the output does not
change and the propagation delay is defined as zero.
For devices with zero or negative set
up times the same
response plot applies, however the abscissa is shifted such
that the value of T0 is no longer the clock transition time.
The same concepts are valid for derivation of metastability
equations for each case: positive, negative or zero set
up
and hold times. To clarify the flip
flop response plot,
Figure 7 illustrates a case in which the propagation delay is
T
P
. Data arrives at time T
A
, allowing the proper set
up time
prior to a clock transition and is maintained at this level for
the specified hold time. Figure 8 is an example in which the
propagation delay is longer than T
P
since the data arrives at
time T
A
, violating the set
up time.
Using the response plot in Figure 6, Stoll
1
developed the
concept of a failure window to facilitate the characterization
of metastability. The value of T
W
(T
D
) is the width of the
window for which a propagation delay of time duration T
D
occurs, and is the range of data input times relative to the
clock input for which a failure will occur. The value of T
D
is the maximum allowable propagation delay; delays longer
than T
D
constitute a failure. The failure window is described
mathematically as:
TW(TD)
TP
10( t) t
(eq. 1)
Where:
T
W
(T
D
) Failure Window Width
T
P
Nominal Propagation Delay
T
D
Delay After Clock That
Constitutes a Failure
Flip
Flop Resolution Time Constant
t
Excess Delay (T
D
T
P
)
T
0
T
MAX
T
A
CLOCK SIGNAL
TIME
DATA SIGNAL
Figure 7. Proper Set
Up and Hold Times
T
0
T
MAX
T
A
CLOCK SIGNAL
DATA SIGNAL
TIME
Figure 8. Violation of Set
Up and Hold Times
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