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参数资料
| 型号： | AN1504D |
| 厂商： | ON SEMICONDUCTOR |
| 英文描述： | Metastability and the ECLinPS Family |
| 中文描述： | 亚稳态和业界的EClinPS家庭 |
| 文件页数： | 5/8页 |
| 文件大小： | 135K |
| 代理商： | AN1504D |
AN1504/D
http://onsemi.com
5
This equation only applies for narrow window widths, i.e.,
those times well up on the response plot of Figure 6.
To summarize, when the set
up and hold times are obeyed
the flip
flop will have a nominal propagation delay, T
P
. If
the data and clock signals arrive such that the set
up and
hold times are violated there will be an excess delay as
indicated in the response plot of Figure 6. This excess delay
is caused by the flip
flop entering the metastable region. For
data signals arriving much later than the clock signal the
flip
flop will not change state, thus the propagation delay is
zero by definition. The window width is the range of input
arrival times relative to the clock for which the output
response does not attain a defined value within the time
period T
D
. Since T
D
represents the maximum allowable
delay, the window width represents the relative range of
input times for which a failure will occur.
Equation 1 can be combined with the industry accepted
definition for system level Mean Time Between Failures
(Equation 2)
2
to derive an equation yielding Mean Time
Between Failures as a function of system design and
semiconductor device parameters.
MTBF
1 (2 * fC* fD* TW(TD))
(eq. 2)
Where:
f
C
f
D
Clock Frequency
Data Frequency
MTBF
1 (2 * fC* fD* TP* 10
( t) )
(eq. 3)
The System Designer can use Equation 3 to address the
issue of metastability. Device values are provided in
Table 2, “ Values for Several Flip
Flops” and T
P
(Nominal Propagation Delay) value is provided in the
device datasheet. MTBF, f
c
and f
d
are system design
parameters. Thus the designer can use this equation to
determine the value of T
D
.
Test Circuitry For Metastable Evaluation
Equation 3 provides the impetus for the design of a
metastability test circuit capable of providing a value of ,
the flip
flop resolution time constant. Transforming this
equation into a “linear” form by taking the logarithm of both
sides yields Equation 4:
log MTBF
Plotting log MTBF versus t yields a line with slope 1/ ,
and log MTBF intercept of
log(2*f
c
*f
d
*T
P
). Thus, the test
circuit must accept the clock and data input frequencies as
a function of t and yield MTBF as an output. The circuit
configuration shown in Figure 9 fulfills these criteria.
The test circuitry can be categorized into five functional
blocks: DUT, adjustable delay portion, comparator section,
counter
set circuitry, and the counter. Starting with the
comparator portion of the circuit, the output of the DUT is
fed into the comparator; if the DUT output falls in the range
V
BB
0.15 V < V
BB
< V
BB
+ 0.15 V, the DUT is defined as
being in a metastable condition (Figure 10).
For DUT output states in the metastable region the
comparator output attains a logic high level. When the DUT
output does not fall within this range it is in a “defined high
or low level,” and the output of the comparator will be at a
logic low level. If the comparator output is at a logic high
level, indicating metastability, the counter
set section sends
out a periodic waveform which increments the counter. If the
DUT is not metastable the output of the “counter
set”
circuitry is constant and the counter (HP
8335A) is not
incremented. The total number of counts over a specified
time period is a measure of MTBF.
log
(2 * fC* fD* TP)
t
(eq. 4)
(V
BB
+ 0.15 V)
Q
Q
ADJUSTABLE DELAY
Q
TRIG
HP
8082A
10E451
CLK 2
CLK 2
D2
D2
D1
D1
Q2
Q1
COUNTER
HP 5335A
COUNTER
DUT
COUNTER
SET
COMPARATOR
Q
Q
HP
8082A
10E131
10E101
CLK 3
Q
D
10E107
HP
8082A
DUT
CLK 1
Q
D
Figure 9. Metastability Test Circuit
(V
BB
0.15 V)
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