参数资料
型号: AP6502SP-13
厂商: Diodes Inc
文件页数: 2/15页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A 8SO
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.925 V ~ 16 V
输入电压: 4.75 V ~ 18 V
PWM 型: 电流模式
频率 - 开关: 340kHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
包装: 标准包装
供应商设备封装: 8-SO 裸露焊盘
其它名称: AP6502SP-13DIDKR
AP6502
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
EP
Pin
Name
BS
IN
SW
GND
FB
COMP
EN
SS
EP
Function
High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET switch. Connect
a 0.01μF or greater capacitor from SW to BS to power the high side switch.
Power Input. IN supplies the power to the IC, as well as the step-down converter switches. Drive IN with a 4.7V
to 18V power source. Bypass IN to GND with a suitably large capacitor to eliminate noise on the input to the IC.
See Input Capacitor.
Power Switching Output. SW is the switching node that supplies power to the output. Connect the output LC
filter from SW to the output load. Note that a capacitor is required from SW to BS to power the high-side switch.
Ground (Connect the exposed pad to Pin 4).
Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage divider
connected to it from the output voltage. The feedback threshold is 0.925V. See Setting the Output Voltage.
Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC network
from COMP to GND. In some cases, an additional capacitor from COMP to GND is required. See
Compensation Components.
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator; low
to turn it off. Attach to IN with a 100k ? pull up resistor for automatic startup.
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-
start period. A 0.1μF capacitor sets the soft-start period to 15ms. To disable the soft-start feature, leave SS
floating.
EP exposed thermal pad connect to Pin 4 GND, not applicable in the SO-8 package.
Functional Block Diagram
+
OVP
2
IN
FB
5
1.1V
-
+
OSCILLATOR
100/340 KHz
RAMP
E
CLK
CURRENT
SENSE
AMPLIFIER
1
BS
0.3 V
-
-
+
Logic
100m ?
3
SW
SS
8
0.925 V
+
+
ERROR
AMPLIFIER
6uA
-
CURRENT
COMPARATOR
100m ?
4
GND
COMP
6
2.5V
+
-
EN OK
LOCKOUT
COMPARATOR
disable
IN < 4.10V
IN
EN
7
+
0.9V
-
SHUTDOWN
COMPARATOR
INTERNAL
REGULATORS
5V
Figure 3 Functional Block Diagram
AP6502
Document Number: DS35423 Rev. 9 - 2
2 of 15
www.diodes.com
January 2013
? Diodes Incorporated
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