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参数资料
型号： APA1000-CGS624B
厂商： Microsemi SoC
文件页数： 161/178页
文件大小： 0K
描述： IC FPGA PROASIC+ 1M 624-CGA
标准包装： 1
系列： ProASICPLUS
RAM 位总计： 202752
输入/输出数： 440
门数： 1000000
电源电压： 2.3 V ~ 2.7 V
安装类型： 通孔
封装/外壳： 624-BCCGA
供应商设备封装： 624-CCGA（32.5x32.5）
ProASICPLUS Flash Family FPGAs
v5.9
2-73
Pin Description
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible
with
standard
LVTTL
and
LVCMOS
specifications. Unused I/O pins are configured as inputs
with pull-up resistors.
NC
No Connect
To maintain compatibility with other Actel ProASICPLUS
products, it is recommended that this pin not be
connected to the circuitry on the board.
GL
Global Pin
Low skew input pin for clock or other global signals. This
pin can be configured with an internal pull-up resistor.
When it is not connected to the global network or the
clock conditioning circuit, it can be configured and used
as a normal I/O.
GLMX
Global Multiplexing Pin
Low skew input pin for clock or other global signals. This
pin can be used in one of two special ways (refer to
Actel’s Using ProASICPLUS Clock Conditioning Circuits).
When the external feedback option is selected for the
PLL block, this pin is routed as the external feedback
source to the clock conditioning circuit.
In applications where two different signals access the
same global net at different times through the use of
GLMXx and GLMXLx macros, this pin will be fixed as one
of the source pins.
This pin can be configured with an internal pull-up
resistor. When it is not connected to the global network
or the clock conditioning circuit, it can be configured and
used as any normal I/O. If not used, the GLMXx pin will
be configured as an input with pull-up.
Dedicated Pins
GND
Ground
Common ground supply voltage.
VDD
Logic Array Power Supply Pin
2.5 V supply voltage.
VDDP
I/O Pad Power Supply Pin
2.5 V or 3.3 V supply voltage.
TMS
Test Mode Select
The TMS pin controls the use of boundary-scan circuitry.
This pin has an internal pull-up resistor.
TCK
Test Clock
Clock input pin for boundary scan (maximum 10 MHz). Actel
recommends adding a nominal 20 k
Ω pull-up resistor to this
pin.
TDI
Test Data In
Serial input for boundary scan. A dedicated pull-up
resistor is included to pull this pin high when not being
driven.
TDO
Test Data Out
Serial output for boundary scan. Actel recommends
adding a nominal 20k
Ω pull-up resistor to this pin.
TRST
Test Reset Input
Asynchronous,
active
low
input pin
for
resetting
boundary-scan circuitry. This pin has an internal pull-up
resistor. For more information, please refer to Power-up
Behavior of ProASICPLUS Devices application note.
Special Function Pins
RCK
Running Clock
A free running clock is needed during programming if
the programmer cannot guarantee that TCK will be
uninterrupted. If not used, this pin has an internal pull-
up and can be left floating.
NPECL
User Negative Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
PPECL
User Positive Input
Provides high speed clock or data signals to the PLL
block. If unused, leave the pin unconnected.
AVDD
PLL Power Supply
Analog VDD should be VDD (core voltage) 2.5 V (nominal)
and be decoupled from GND with suitable decoupling
capacitors to reduce noise. For more information, refer
to Actel’s Using ProASICPLUS Clock Conditioning Circuits
application note. If the clock conditioning circuitry is not
used in a design, AVDD can either be left floating or tied
to 2.5 V.
AGND
PLL Power Ground
The analog ground can be connected to the system
ground. For more information, refer to Actel’s Using
ProASICPLUS Clock Conditioning Circuits application note.
If the PLLs or clock conditioning circuitry are not used in
a design, AGND should be tied to GND.
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相关代理商/技术参数
参数描述
APA1000-CGS624M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 624-Pin CCGA 制造商:Microsemi Corporation 功能描述:APA1000-CGS624M - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA PROASIC+ 1M 624CCGA
APA1000-CQ208B 功能描述:IC FPGA PROASIC+ 1M 208-CQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27）
APA1000-CQ208M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 208-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 1M GATES 180MHZ 0.22UM 2.5V 208CQFP - Trays
APA1000-CQ352B 功能描述:IC FPGA PROASIC+ 1M 352-CQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASICPLUS 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27）
APA1000-CQ352M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 1M Gates 180MHz 0.22um Technology 2.5V 352-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 1M GATES 180MHZ 0.22UM 2.5V 352CQFP - Trays
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