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参数资料
型号： APA300-PQ208I
厂商： Microsemi SoC
文件页数： 146/178页
文件大小： 0K
描述： IC FPGA PROASIC+ 300K 208-PQFP
标准包装： 24
系列： ProASICPLUS
RAM 位总计： 73728
输入/输出数： 158
门数： 300000
电源电压： 2.3 V ~ 2.7 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 208-BFQFP
供应商设备封装： 208-PQFP（28x28）
ProASICPLUS Flash Family FPGAs
v5.9
1-3
Live at Power-Up
The Actel flash-based ProASICPLUS devices support
Level 0 of the live at power-up (LAPU) classification
standard. This feature helps in system component
initialization,
executing
critical
tasks
before
the
processor wakes up, setting up and configuring memory
blocks, clock generation, and bus activity management.
The LAPU feature of flash-based ProASICPLUS devices
greatly simplifies total system design and reduces total
system cost, often eliminating the need for complex
programmable logic device (CPLD) and clock generation
PLLs that are used for this purpose in a system. In
addition, glitches and brownouts in system power will
not corrupt the ProASICPLUS device's flash configuration,
and unlike SRAM-based FPGAs, the device will not have
to be reloaded when system power is restored. This
enables the reduction or complete removal of the
configuration
PROM,
expensive
voltage
monitor,
brownout detection, and clock generator devices from
the PCB design. Flash-based ProASICPLUS devices simplify
total system design, and reduce cost and design risk,
while increasing system reliability and improving system
initialization time.
Flash Switch
Unlike SRAM FPGAs, ProASICPLUS uses a live-at-power-up
ISP flash switch as its programming element.
In the ProASICPLUS flash switch, two transistors share the
floating
gate,
which
stores
the
programming
information. One is the sensing transistor, which is only
used for writing and verification of the floating gate
voltage. The other is the switching transistor. It can be
used in the architecture to connect/separate routing nets
or to configure logic. It is also used to erase the floating
gate (Figure 1-2 on page 1-2).
Logic Tile
The logic tile cell (Figure 1-3) has three inputs (any or all
of which can be inverted) and one output (which can
connect to both ultra-fast local and efficient long-line
routing resources). Any three-input, one-output logic
function (except a three-input XOR) can be configured as
one tile. The tile can be configured as a latch with clear
or set or as a flip-flop with clear or set. Thus, the tiles can
flexibly map logic and sequential gates of a design.
Figure 1-3 Core Logic Tile
Local Routing
In 1
In 2 (CLK)
In 3 (Reset)
Efficient Long-Line Routing
相关PDF资料
PDF描述
APA300-PQG208I IC FPGA PROASIC+ 300K 208-PQFP
GEC43DTEN CONN EDGECARD 86POS .100 EYELET
GEC43DTEH CONN EDGECARD 86POS .100 EYELET
ACC50DRTN CONN EDGECARD 100PS .100 DIP SLD
ACC65DRTF CONN EDGECARD 130PS .100 DIP SLD
相关代理商/技术参数
参数描述
APA300-PQ208M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 300K Gates 180MHz 0.22um Technology 2.5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 208PQFP - Trays
APA300-PQ208MX319 制造商:Microsemi Corporation 功能描述:PROASICPLUS? 300K GATES 5MHZ MILITARY FLASH 2.5V 208 QFP - Trays
APA300-PQ896A 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:Automotive-Grade ProASIC Flash Family FPGAs
APA300-PQB 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA300-PQES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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