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参数资料
| 型号： | AS1339 EB |
| 厂商： | ams |
| 文件页数： | 23/26页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AS1339 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 3，非隔离 |
| 输出电压： | 0.8 ~ 3.75 V，2.85V，2.85V |
| 电流 - 输出： | 650mA |
| 输入电压： | 2.7 ~ 5.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 2MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | AS1339 |
AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Layout Considerations
Please carefully observe that large peak currents of up to 1.1A and high switching frequencies will make the PCB lay-
out a very important part of the system performance and compliance. A proper PCB design will minimize electro mag-
netic interference (EMI) as well as voltage gradients in the ground plane, which both can result in application
instabilities. Please closely follow the guidelines as mentioned below.
- Keep the power traces as short and wide as possible (IN1A, IN1B, IN2, LX, PAA, PAB, PGND)
- Place all capacitors as close as possible to the pins of the device
- Avoid voltage gradients in the ground plane
- The negative terminals of COUT and CIN1/CIN2 are kept as close as possible to each other. It is recommended
to connect these terminals directly to PGND at a star point.
- The current path between pins IN1A/IN1B (C3/C4) and pin PGND (A4) via CIN1 is routed very short
- The current path between pins PAB/PAA (D3/D4) and pin PGND (A4) via COUT is routed very short
- The connection between LX (B4) and pins PAB/PAA (D3/D4) via the coil (L) is routed very short
- To keep the cross-coupling between the LDOs and DC/DC minimized, in regard to supply ripple and noise induc-
tion, the IN1 and IN2 path are separated. Both power inputs should be connected at a star point directly at the
main supply
- To prevent voltage gradients between AGND (A2) and PGND (A4), these pins are connected via a short, low
ohmic, trace to each other.
Figure 54. Layout for Space Limited Applications
Revision 1.05
22 - 25
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| AS133R0HLF | 制造商:TT Electronics / IRC 功能描述:AS133R0HLF |
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