参数资料
型号: AS5030-ATSU
厂商: ams
文件页数: 9/44页
文件大小: 0K
描述: IC ENCODER ROTARY 8-BIT 16-TSSOP
应用说明: AS5000 Series Magnet Selection Guide
AS5000 Series Magnets for Extended Vertical Range
标准包装: 96
传感范围: 23.6mT ~ 44.5mT
类型: 线性,旋转编码器 - 可编程
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 14mA
电流 - 输出(最大): 4mA
输出类型: 数字,PWM
特点: 可编程
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
AS5030
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.8 8-bit PWM Output
Symbol
Parameter
Conditions
Min
Typ
Max
Units
N PWM
PWM resolution
8
2
bit
μs/step
Over full temperature range
Digital hysteresis
PW MIN
PW MAX
PW P
f PWM
Hyst
PWM pulse width
PWM pulse width
PWM period
PWM frequency
2
Angle = 0° (00 H )
Angle = 358.6° (FF H )
1
1 / PWM period
At change of rotation direction
1.66
427
428
2.26
578
581
1.72
1
2.85
731
734
μs
μs
μs
kHz
bit
1. The tolerance of the absolute PWM pulse width and frequency can be eliminated by using the duty cycle t ON /(t ON +t OFF ) for angle
measurement (see 1-Wire PWM Connection on page 16) .
2. Hysteresis may be temporarily disabled by software (see 16-bit Write Command on page 24) .
6.9 Serial 8-bit Output
3-wire Interface.
Symbol
f CLK
t CLK
f clk,P
Parameter
Clock frequency
Clock frequency
Conditions
Normal operation
During OTP programming
Min
166.6
250
Typ
Max
6
500
Units
MHz
ns
kHz
2-wire Interface.
Digital hysteresis
Symbol
f CLK
t CLK
f clk,P
t TO
Hyst
Parameter
Clock frequency
Clock frequency
Synchronization timeout
1
Conditions
Normal operation
During OTP programming
Rising edge of CLK to internally generated
chip select on pin DX
At change of rotation direction
Min
0.1
166.6
250
16.6
Typ
27
1
Max
6
10,000
500
34.3
Units
MHz
ns
kHz
ms
bit
1. Hysteresis may be temporarily disabled by software.
www.ams.com/AS5030
Revision 2.4
9 - 44
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