参数资料
型号: AS5045-ASST
厂商: ams
文件页数: 11/34页
文件大小: 0K
描述: IC ENCODER PROG 12-BIT 16-SSOP
应用说明: AS5000 Series Magnet Selection Guide
AS5000 Series Magnets for Extended Vertical Range
标准包装: 1
传感范围: 45mT ~ 75mT
类型: 线性,旋转编码器 - 可编程
电源电压: 3 V ~ 3.6 V,4.5 V ~ 5.5 V
电流 - 电源: 21mA
电流 - 输出(最大): 4mA
输出类型: 数字式,PWM,12 位串行
特点: 可编程
工作温度: -40°C ~ 125°C
封装/外壳: 16-SSOP(0.209",5.30mm 宽)
供应商设备封装: 16-SSOP
包装: 标准包装
产品目录页面: 804 (CN2011-ZH PDF)
其它名称: AS5045-ASSTDKR
AS5045
Data Sheet
Figure 3. Integral and Differential Non-linearity (example)
4095 α 12bit code
Actual curve
4095
2
1
TN
DNL+1LSB
Ideal curve
2048
0
INL
0.09°
2048
0
0 °
180°
360 °
α [degrees]
Integral Non-Linearity (INL) is the maximum deviation between actual position and indicated position.
Differential Non-Linearity (DNL) is the maximum deviation of the step length from one position to the next.
Transition Noise (TN) is the repeatability of an indicated position
6.7 Timing Characteristics
6.7.1
Synchronous Serial Interface (SSI)
(operating conditions: T amb = -40 to +125°C, VDD5V = 3.0~3.6V (3V operation) VDD5V = 4.5~5.5V (5V operation)
unless otherwise noted)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Data output activated
(logic high)
First data shifted to output
register
Start of data output
t DO active
t CLK FE
T CLK / 2
500
500
100
ns
ns
ns
Time between falling edge of CSn and data
output activated
Time between falling edge of CSn and first
falling edge of CLK
Rising edge of CLK shifts out one bit at a
time
Data output valid
t DO valid
357
375
394
ns
Time between rising edge of CLK and data
output valid
Data output tristate
Pulse width of CSn
t DO tristate
t CSn
500
100
ns
ns
After the last bit DO changes back to
“tristate”
CSn = high; To initiate read-out of next
angular position
Read-out frequency
f CLK
>0
1
MHz
Clock frequency to read out serial data
www.austriamicrosystems.com
Revision 1.7
10 – 33
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