参数资料
型号: AS7C25512PFD36A-133TQIN
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: SRAM
英文描述: 512K X 36 STANDARD SRAM, 3.8 ns, PQFP100
封装: 14 X 20 MM, LEAD FREE, TQFP-100
文件页数: 19/19页
文件大小: 523K
代理商: AS7C25512PFD36A-133TQIN
2/10/05, v. 1.2
Alliance Semiconductor
9 of 19
AS7C25512PFD32A
AS7C25512PFD36A
DC electrical characteristics
LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10
A.
*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**VIL min = -1.5 for pulse width less than 0.2 X tCYC
IDD operating conditions and maximum limits
Parameter
Sym
Conditions
Min
Max
Unit
Input leakage current
|ILI|VDD = Max, 0V < VIN < VDD
-2
2
A
Output leakage current
|ILO|OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
-2
2
A
Input high (logic 1) voltage
VIH
Address and control pins
1.7*
VDD+0.3
V
I/O pins
1.7*
VDDQ+0.3
V
Input low (logic 0) voltage
VIL
Address and control pins
-0.3**
0.7
V
I/O pins
-0.3**
0.7
V
Output high voltage
VOH
IOH = –4 mA, VDDQ = 2.375V
1.7
V
Output low voltage
VOL
IOL = 8 mA, VDDQ = 2.625V
0.7
V
Parameter
Sym
Conditions
-166
-133
Unit
Operating power supply current1
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
ICC
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,
IOUT = 0 mA, ZZ < VIL
290
270
mA
Standby power supply current
ISB
All VIN ≤ 0.2V or > VDD – 0.2V, Deselected,
f = fMax, ZZ < VIL
85
75
mA
ISB1
Deselected, f = 0, ZZ
< 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
40
ISB2
Deselected, f = fMax, ZZ ≥ VDD – 0.2V,
all VIN ≤ VIL or ≥ VIH
40
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