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参数资料
| 型号： | AS7C25512PFD36A-133TQIN |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 512K X 36 STANDARD SRAM, 3.8 ns, PQFP100 |
| 封装： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件页数： | 8/19页 |
| 文件大小： | 523K |
| 代理商： | AS7C25512PFD36A-133TQIN |
AS7C25512PFD32A
AS7C25512PFD36A
2/10/05, v. 1.2
Alliance Semiconductor
16 of 19
AC test conditions
Notes
1
For test conditions, see “AC test conditions”, Figures A, B, and C.
2
This parameter is measured with output load condition in Figure C.
3
This parameter is sampled but not 100% tested.
4tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
5tCH is measured as high if above VIH, and tCL is measured as low if below VIL.
6
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
Write refers to GWE, BWE, and BW[a:d].
8
Chip select refers to CE0, CE1, and CE2.
Z0 = 50
DOUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+2.5V
Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.
Input pulse level: GND to 2.5V. See Figure A.
Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.
Input and output timing reference levels: 1.25V.
VL = VDDQ/2
Thevenin equivalent:
353
/1538
5 pF*
319
/1667
DOUT
GND
Figure C: Output load(B)
*including scope
and jig capacitance
+2.5V
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| AS7C25512PFD36A-166TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM |
| AS7C25512PFD36A-166TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM |
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| AS7C25512PFD36A-166TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 pipelined burst synchronous SRAM |
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