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参数资料
| 型号： | AS7C33512PFS16A-133BI |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 512K X 16 STANDARD SRAM, 10 ns, PBGA119 |
| 封装： | 14 X 20 MM, BGA-119 |
| 文件页数： | 1/14页 |
| 文件大小： | 370K |
| 代理商： | AS7C33512PFS16A-133BI |
April 2002
Preliminary
Copyright Alliance Semiconductor. All rights reserved.
AS7C33512PFS16A
AS7C33512PFS18A
3.3V 512K
× 16/18 pipeline burst synchronous SRAM
4/15/02;
v.1.5
Alliance Semiconductor
1 of 14
Features
Organization: 524,288 words × 16 or 18 bits
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/3.8/4.0/5.0 ns
Fast OE access time: 3.5/3.8/4.0/5.0 ns
Fully synchronous register-to-register operation
Single register “Flow-through” option
Single-cycle deselect
- Dual-cycle deselect also available (AS7C33512PFD16A/
AS7C33512PFD18A)
Available in both 2 chip enable and 3 chip enable
- 2 CE part number is AS7C33512PFS16A or AS7C33512PFS18A2
Pentium1 compatible architecture and timing
Asynchronous output enable control
Available in 100-pin TQFP and 119-ball BGA package
Byte write enables
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate VDDQ
30 mW typical standby power in power down mode
NTD1 pipeline architecture available
(AS7C33512NTD16A/AS7C33512NTD18A)
1. Pentium is a registered trademark of Intel Corporation. NTD is a
trademark of Alliance Semiconductor Corporation. All trademarks men-
tioned in this document are the property of their respective owners.
Selection guide
–166
–150
–133
–100
Units
Minimum cycle time
6
6.6
7.5
10
ns
Maximum pipelined clock frequency
166
150
133
100
MHz
Maximum pipelined clock access time
3.5
3.8
4
5
ns
Maximum operating current
475
450
425
325
mA
Maximum standby current
130
110
100
90
mA
Maximum CMOS standby current (DC)
30
mA
Logic block diagram
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
19
17
19
A[18:0]
19
Address
D
Q
CS
CLK
register
512K × 16/18
Memory
array
16/18
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
2
CE0
CE1
CE2
BWb
BWa
OE
ZZ
OE
FT
CLK
BWE
GWE
16/18
DQ[a,b]
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AS7C33512PFS18A | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
| AS7C33512PFS18A-133TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 512K x 18 pipeline burst synchronous SRAM |
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