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参数资料
| 型号： | AS7C3364FT36B-65TQCN |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 64K X 36 STANDARD SRAM, 6.5 ns, PQFP100 |
| 封装： | 14 X 20 MM, LEAD FREE, TQFP-100 |
| 文件页数： | 8/19页 |
| 文件大小： | 417K |
| 代理商： | AS7C3364FT36B-65TQCN |
AS7C3364FT32B
2/8/05; v.1.2
Alliance Semiconductor
P. 16 of 19
AS7C3364FT36B
AC test conditions
Z0 = 50
DOUT
50
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
Input pulse level: GND to 3V. See Figure A.
Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
for 2.5V I/O
353
/ 1538
5 pF*
319
/ 1667
DOUT
GND
Figure C: Output load (B)
*including scope
and jig capacitanc
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
Notes
1
For test conditions, see AC Test Conditions, Figures A, B, C.
2
This parameter measured with output load condition in Figure C.
3
This parameter is sampled, but not 100% tested.
4tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
5
tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times for all rising edges of CLK when chip is enabled.
7
Write refers to GWE, BWE, BW[a:d].
8
Chip select refers to CE0, CE1, CE2
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相关代理商/技术参数 |
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| AS7C3364FT36B-65TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Flow Through Synchronous SRAM |
| AS7C3364FT36B-65TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:3.3V 64K x 32/36 Flow Through Synchronous SRAM |
| AS7C3364FT36B-75TQC | 制造商:Alliance Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 2.25M-Bit 64K x 36 7.5ns 100-Pin TQFP |
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