参数资料
型号: AS7C3364FT36B-80TQC
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: SRAM
英文描述: 64K X 36 STANDARD SRAM, 8 ns, PQFP100
封装: 14 X 20 MM, TQFP-100
文件页数: 1/19页
文件大小: 417K
代理商: AS7C3364FT36B-80TQC
February 2005
Copyright Alliance Semiconductor. All rights reserved.
AS7C3364FT32B
3.3V 64K
× 32/36 Flow Through Synchronous SRAM
2/8/05; v.1.2
Alliance Semiconductor
P. 1 of 19
AS7C3364FT36B
Features
Organization: 65,536 words × 32 or 36 bits
Fast clock to data access: 6.5/7.5/8.0/10.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous flow through operation
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and Global write
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate VDDQ
Linear or interleaved burst control
Snooze mode for reduced power standby
Common data inputs and data outputs
Selection guide
–65
-75
-80
-10
Units
Minimum cycle time
7.5
8.5
10
12
ns
Maximum clock access time
6.5
7.5
8.0
10.0
ns
Maximum operating current
275
250
215
185
mA
Maximum standby current
90
85
75
mA
Maximum CMOS standby current (DC)
30
mA
Logic block diagram
Q0
Q1
64K × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQd
CLK
DQ
Byte write
registers
register
DQc
CLK
DQ
Byte write
registers
DQb
CLK
DQ
Byte write
registers
DQa
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
buffer
Input
registers
Power
down
DQ[a:d]
4
36/32
18
16
18
18
GWE
BWE
BWd
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BWc
BWb
BWa
OE
ZZ
LBO
OE
CLK
36/32
A[17:0]
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