参数资料
型号: AS7C3364FT36B-80TQC
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: SRAM
英文描述: 64K X 36 STANDARD SRAM, 8 ns, PQFP100
封装: 14 X 20 MM, TQFP-100
文件页数: 17/19页
文件大小: 417K
代理商: AS7C3364FT36B-80TQC
AS7C3364FT32B
2/8/05; v.1.2
Alliance Semiconductor
P. 7 of 19
AS7C3364FT36B
Synchronous truth table[4]
CE01
1 X = don’t care, L = low, H = high
CE1
CE2
ADSP
ADSC
ADV
WRITE[2]
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE
OE
Address accessed
CLK
Operation
DQ
HXXX
L
X
NA
L to H
Deselect
Hi
Z
L
X
L
X
NA
L to H
Deselect
Hi
Z
L
X
H
L
X
NA
L to H
Deselect
Hi
Z
L
X
H
L
X
NA
L to H
Deselect
Hi
Z
L
X
H
L
X
NA
L to H
Deselect
Hi
Z
L
H
L
X
L
External
L to H
Begin read
Q
L
H
L
X
H
External
L to H
Begin read
Hi
Z
L
H
L
H
L
X
H
L
External
L to H
Begin read
Q
L
H
L
H
L
X
H
External
L to H
Begin read
Hi
Z
XXXHH
L
H
L
Next
L to H
Continue read
Q
XXXHH
L
H
Next
L to H
Continue read
Hi
Z
XXXHH
H
L
Current
L to H
Suspend read
Q
XXXHH
H
Current
L to H
Suspend read
Hi
Z
HXXXH
L
H
L
Next
L to H
Continue read
Q
HXXXH
L
H
Next
L to H
Continue read
Hi
Z
HXXXH
H
L
Current
L to H
Suspend read
Q
HXXXH
H
Current
L to H
Suspend read
Hi
Z
L
H
L
H
L
X
L
X
External
L to H
Begin write
D3
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
XXXHH
L
X
Next
L to H
Continue write
D
HXXXH
L
X
Next
L to H
Continue write
D
XXXHH
H
L
X
Current
L to H
Suspend write
D
HXXXH
H
L
X
Current
L to H
Suspend write
D
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