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参数资料
| 型号： | AT18F010-30XU |
| 厂商： | Atmel |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC FLASH CONFIG 1MBIT 20-TSSOP |
| 产品变化通告： | AT18F Family Obsolescence 06/Feb/2012 |
| 标准包装： | 74 |
| 可编程类型： | 闪存 |
| 存储容量： | 1Mb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 609 (CN2011-ZH PDF) |
6
3672A–CNFG–1/08
AT18F010/002/040/080 [Preliminary]
6.
Pin Description
6.1
DATA (D0)
Open-collector bi-directional data pin. This pin has an internal 20 K
pull-up resistor.
6.2
CLK
Clock input. Used to increment the internal address and bit counter for reading and program-
ming. This pin has an internal 20 K
pull-up resistor.
6.3
RESET/OE
Output Enable (active High) and RESET (active Low). A Low level on RESET/OE resets both
the address and bit counters. A High level (with CE Low) enables the data output driver. This pin
has an internal 20 K
pull-up resistor.
6.4
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. This pin has an internal 20 K
pull-up resistor.
6.5
CF
Configuration Pulse (open-drain output). Allows JTAG CONFIG instruction to initiate FPGA con-
figuration without powering down the FPGA. This is an open-drain output that is pulsed Low by
the JTAG CONFIG command.
Table 6-1.
Pin Descriptions
Name
Type
20-lead TSSOP
DATA
I/O
1
CLK
I
3
RESET/OE
I
8
CE
I10
CF
I7
CEO
O13
TMS
I
5
TCK
I
6
TDI
I
4
TDO
O
17
VCCINT
I
18
NC
-
2, 9, 12, 14, 15, 16
VCCO
Power Supply
19
GND
Ground
11
VCCJ
Power Supply
20
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