参数资料
| 型号： | ISL6323ACRZ |
| 厂商： | Intersil |
| 文件页数： | 17/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR SYNC BUCK DL 48QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6323A
Serial VID Interface (SVI)
The on-board Serial VID interface (SVI) circuitry allows the
processor to directly drive the core voltage and Northbridge
voltage reference level within the ISL6323A. The SVC and
SVD states are decoded with direction from the PWROK and
VFIXEN inputs as described in the sections that follow. The
ISL6323A uses a digital to analog converter (DAC) to
generate a reference voltage based on the decoded SVI
value. See Figure 7 for a simple SVI interface timing
diagram.
PRE-PWROK METAL VID
Typical motherboard start-up occurs with the VFIXEN input
low. The controller decodes the SVC and SVD inputs to
determine the Pre-PWROK metal VID setting. Once the
POR circuitry is satisfied, the ISL6323A begins decoding the
inputs per Table 2. Once the EN input exceeds the rising
enable threshold, the ISL6323A saves the Pre-PWROK
metal VID value in an on-board holding register and passes
this target to the internal DAC circuitry.
The Pre-PWROK metal VID code is decoded and latched on
the rising edge of the enable signal. Once enabled, the
ISL6323A passes the Pre-PWROK metal VID code on to
internal DAC circuitry. The internal DAC circuitry begins to
ramp both the VDD and VDDNB planes to the decoded Pre-
PWROK metal VID output level. The digital soft-start circuitry
actually stair steps the internal reference to the target
gradually over a fix interval. The controlled ramp of both
output voltage planes reduces in-rush current during the
soft-start interval. At the end of the soft-start interval, the
VDDPWRGD output transitions high indicating both output
planes are within regulation limits
If the EN input falls below the enable falling threshold, the
ISL6323A ramps the internal reference voltage down to near
zero. The VDDPWRGD deasserts with the loss of enable.
The VDD and VDDNB planes will linearly decrease to near
zero.
TABLE 3. VFIXEN VID CODES
OUTPUT VOLTAGE
TABLE 2. PRE-PWROK METAL VID CODES
OUTPUT VOLTAGE
SVC
0
SVD
0
(V)
1.4
SVC
0
0
SVD
0
1
(V)
1.1
1.0
0
1
1
1
0
1
1.2
1.0
0.8
1
0
0.9
1
1
0.8
VFIX MODE
In VFIX Mode, the SVC, SVD and VFIXEN inputs are fixed
external to the controller through jumpers to either GND or
VDDIO. These inputs are not expected to change, but the
1
2
3
4
5
6
7
8
9
10
11
12
VCC
SVC
SVD
ENABLE
PWROK
METAL_VI D
V_SVI
METAL_VI D
V_SVI
VDD AND VDDNB
VDDPWRGD
VFIXEN
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID STAR-TUP
17
FN6878.1
May 12, 2010
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