参数资料
| 型号： | ISL6323ACRZ |
| 厂商： | Intersil |
| 文件页数： | 31/36页 |
| 文件大小： | 0K |
| 描述： | IC PWM CTRLR SYNC BUCK DL 48QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6323A
-------------------------------- > f 0
Case 1:
1
2 ? π ? L ? C
problems with too much phase shift below the system
bandwidth.
R C = R FB ? ----------------------------------------------------------
2 ? π ? V PP ? R FB ? f 0
R 1 = R FB ? --------------------------------------------
C 1 = --------------------------------------------
2 ? π ? f 0 ? V P-P ? L ? C
0.66 ? V IN
0.66 ? V IN
C C = ----------------------------------------------------
.
C ? ESR
L ? C – C ? ESR
L ? C – C ? ESR
R FB
-------------------------------- ≤ f 0 < -------------------------------------
V PP ? ( 2 ? π ) 2 ? f 02 ? L ? C
R C = R FB ? -----------------------------------------------------------------
( 2 ? π ) 2 ? f 02 ? V PP ? R FB ? L ? C
C 2 = -----------------------------------------------------------------------------------------------------
HF ? ( L ? C ) ? R FB ? V P-P
( 2 ? π ) 2 ? f ? f
V P-P ? ? 2 π ? ? f 0 ? f HF ? L ? C ? R FB
R C = ------------------------------------------------------------------------------------------
0.75 ? V ? ( 2 ? π ? f HF ? L ? C – 1 )
Case 2:
1 1
2 ? π ? L ? C 2 ? π ? C ? ESR
0.66 ? V IN
0.66 ? V IN
C C = -------------------------------------------------------------------------------------
(EQ. 51)
0
? ?
IN
2
0.75 ? V IN
(EQ. 52)
f 0 > -------------------------------------
R C = R FB ? ----------------------------------------------
( 2 ? π ) 2 ? f 0 ? f HF ? ( L ? C ) ? R FB ? V P-P
Case 3:
1
2 ? π ? C ? ESR
2 ? π ? f 0 ? V P-P ? L
0.66 ? V IN ? ESR
0.75 ? V IN ? ( 2 ? π ? f HF ? L ? C – 1 )
C C = -----------------------------------------------------------------------------------------------------
In the solutions to the compensation equations, there is a
2 ? π ? V PP ? R FB ? f 0 ? L
0.66 ? V IN ? ESR ? C
C C = ----------------------------------------------------------------
Compensation Without Loadline Regulation
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 23, provides the
necessary compensation.
C 2
single degree of freedom. For the solutions presented in
Equation 53, R FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 53.
In Equation 53, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V P-P is the
peak-to-peak sawtooth signal amplitude as described in
.
-------------------------------- > f 0
R C
C C
COMP
Case 1:
1
2 ? π ? L ? C
R C = R FB ? ----------------------------------------------------------
FB
2 ? π ? f 0 ? V P-P ? L ? C
0.66 ? V IN
2 ? π ? V P-P ? R FB ? f 0
-------------------------------- ≤ f 0 < -------------------------------------
C 1
R 1
R FB
VSEN
ISL6323A
Case 2:
0.66 ? V IN
C C = ------------------------------------------------------
1 1
2 ? π ? L ? C 2 ? π ? C ? ESR
V PP ? ( 2 ? π ) 2 ? f 02 ? L ? C
R C = R FB ? -----------------------------------------------------------------
( 2 ? π ) 2 ? f 02 ? V P-P ? R FB ? L ? C
FIGURE 23. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
0.66 ? V IN
0.66 ? V IN
C C = ---------------------------------------------------------------------------------------
(EQ. 53)
f 0 > -------------------------------------
R C = R FB ? ----------------------------------------------
2 ? π ? V P-P ? R FB ? f 0 ? L
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f HF . This pole can be used for
added noise rejection or to assure adequate attenuation at the
error-amplifier high-order pole and zero frequencies. A good
general rule is to choose f HF = 10f 0 , but it can be higher if
desired. Choosing f HF to be lower than 10f 0 can cause
31
Case 3:
1
2 ? π ? C ? ESR
2 ? π ? f 0 ? V P-P ? L
0.66 ? V IN ? ESR
0.66 ? V IN ? ESR ? C
C C = ------------------------------------------------------------------
FN6878.1
May 12, 2010
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