AT49LV8011 PDF资料下载(2/18 页)8-megabit 3-volt Flash Memory(8M位 3V闪速存储器)

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参数资料

型号：	AT49LV8011
厂商：	Atmel Corp.
英文描述：	8-megabit 3-volt Flash Memory(8M位 3V闪速存储器)
中文描述：	8兆位3伏的快闪记忆体（800万位3V的闪速存储器）
文件页数：	2/18页
文件大小：	322K
代理商：	AT49LV8011

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AT49BV/LV8011(T)

contention. This device can be read or reprogrammed

using a single 2.7V power supply, making it ideally suited

for in-system programming.

The device powers on in the read mode. Command

sequences are used to place the device in other operation

modes such as Program and Erase. The device has the

capability to protect the data in any sector. Once the data

protection for a given sector is enabled, the data in that

sector cannot be changed using input levels between

ground and V

The device is segmented into two memory planes. Reads

from memory plane B may be performed even while pro-

gram or erase functions are being executed in memory

plane A and vice versa. This operation allows improved

system performance by not requiring the system to wait for

a program or erase operation to complete before a read is

performed. To further increase the flexibility of the device, it

contains an Erase Suspend feature. This feature will put

the Erase on hold for any amount of time and let the user

read data from or program data to any of the remaining

sectors within the same memory plane. There is no reason

to suspend the erase operation if the data to be read is in

the other memory plane. The end of a program or an Erase

cycle is detected by the Ready/Busy pin, Data polling, or by

the toggle bit.

A VPP pin is provided to improve program/erase times.

This pin can be tied to V

. To take advantage of faster

programming and erasing, the pin should supply 4.5 to

5.5 volts during program and erase operations.

A 6-byte command (bypass unlock) sequence to remove

the requirement of entering the 3-byte program sequence

is offered to further improve programming time. After enter-

ing the 6-byte code, only single pulses on the write control

lines are required for writing into the device. This mode

(single-pulse byte/word program) is exited by powering

down the device, or by pulsing the RESET pin low for a

minimum of 50 ns and then bringing it back to V

. Erase

and Erase Suspend/Resume commands will not work while

in this mode; if entered they will result in data being pro-

grammed into the device. It is not recommended that the

6-byte code reside in the software of the final product but

only exist in external programming code.

The BYTE pin controls whether the device data I/O pins

operate in the byte or word configuration. If the BYTE pin is

set at logic

“

”

, the device is in word configuration,

I/O0 - I/O15 are active and controlled by CE and OE.

If the BYTE pin is set at logic

“

”

, the device is in byte con-

figuration, and only data I/O pins I/O0 - I/O7 are active and

controlled by CE and OE. The data I/O pins I/O8 - I/O14

are tri-stated, and the I/O15 pin is used as an input for the

LSB (A-1) address function.

CBGA Top View

RDY/BUSY

A18

I/O2

I/O10

I/O11

I/O3

VSS

A17

I/O0

I/O8

I/O9

I/O1

RESET

VPP

I/O5

I/O12

VCC

I/O4

A10

A11

I/O7

I/O14

I/O13

I/O6

A13

A12

A14

A15

A16

BYTE

I/A-1

VSS

TSOP Top View

Type 1

A15

A14

A13

A12

A11

A10