参数资料
型号: AT80C51RD2-SLRUM
厂商: Atmel
文件页数: 2/81页
文件大小: 0K
描述: IC MCU 80C51 HI PERFORM 44PLCC
产品培训模块: MCU Product Line Introduction
标准包装: 1
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器类型: ROMless
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 标准包装
其它名称: AT80C51RD2-SLRUMDKR
10
4113D–8051–01/09
AT80C51RD2
Figure 6-2.
Mode Switching Waveforms
The X2 bit in the CKCON0 register (see Table 6-1) allows to switch from 12 clock periods per
instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of
Hardware Config Byte (HCB). By default, Standard mode is activated. Setting the X2 bit acti-
vates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UARTX2, PCAX2 and WDX2 bits in the CKCON0 register (Table 6-1)
allow to switch from standard peripheral speed (12 clock periods per peripheral clock cycle) to
fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in
X2 mode.
Table 6-1.
CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
XTAL1:2
CPU Block
X2 Bit
X2 Mode
STD Mode
F
OSC
XTAL1
765
4321
0
-
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic
Description
7-
Reserved
Do not set this bit.
6WDX2
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
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