参数资料
型号: AT80C51RD2-SLRUM
厂商: Atmel
文件页数: 3/81页
文件大小: 0K
描述: IC MCU 80C51 HI PERFORM 44PLCC
产品培训模块: MCU Product Line Introduction
标准包装: 1
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器类型: ROMless
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 标准包装
其它名称: AT80C51RD2-SLRUMDKR
11
4113D–8051–01/09
AT80C51RD2
Reset Value = 0000 000’HCB.X2’b (see Hardware Config Byte)
Not bit addressable
5
PCAX2
Programmable Counter Array clock (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4SIX2
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU
clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3T2X2
Timer 2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2T1X2
Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
1T0X2
Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
0X2
CPU clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the
peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual
peripherals "X2" bits.
Programmed by hardware after Power-up regarding Hardware Config Byte (HCB).
Bit
Number
Bit
Mnemonic
Description
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