参数资料
型号: AT80C51RD2-SLRUM
厂商: Atmel
文件页数: 33/81页
文件大小: 0K
描述: IC MCU 80C51 HI PERFORM 44PLCC
产品培训模块: MCU Product Line Introduction
标准包装: 1
系列: 80C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器类型: ROMless
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 标准包装
其它名称: AT80C51RD2-SLRUMDKR
39
4113D–8051–01/09
AT80C51RD2
Table 11-4.
SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
765
4321
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic
Description
7FE
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6SM1
Serial port Mode bit 1
SM1ModeDescriptionBaud Rate
0
0Shift Registerf
CPU PERIPH/6
1
18-bit UARTVariable
0
29-bit UARTf
CPU PERIPH /32 or /16
1
39-bit UARTVariable
5SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually
mode 1. This bit should be cleared in mode 0.
4REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
o transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2RB8
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2=0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop
bit in the other modes.
0RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 11-2. and Figure
11-3. in the other modes.
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