参数资料
型号: AT83EB5114XXXTGRIL
厂商: ATMEL CORP
元件分类: 微控制器/微处理器
英文描述: Low-pin-count 8-bit microcontroller with A/D converter
中文描述: 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDSO20
封装: SO-20
文件页数: 60/95页
文件大小: 1126K
代理商: AT83EB5114XXXTGRIL
60
4311A–8051–01/05
ADC Converter
Operation
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
The busy flag ADSST(ADCON.3) remains set as long as an A/D conversion is running.
After completion of the A/D conversion, it is cleared by hardware. When a conversion is
running, this flag can be read only, a write has no effect.
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is
available in ADDH and ADDL, it is cleared by software. If the bit EADC (IE0.6) is set, an
interrupt occur when flag ADEOC is set (see Figure 30). Clear this flag for re-arming the
interrupt.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel
selection.
Before starting normal power reduction modes the ADC conversion has to be
completed.
Table 45.
Selected Analog Input
Voltage Conversion
When the ADCIN is equal to VAREF the ADC converts the signal to 3FFh (full scale). If
the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between
VAREF and VAGND are a straight-line linear conversion. All other voltages will result in
3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range.
Clock Selection
The maximum clock frequency for ADC (CONV_CK for Conversion Clock) is defined in
the Section “AC Parameters”, page 88. A prescaler is featured to generate the
CONV_CK clock from the oscillator frequency. The prescaler value PRS[6:0] is defined
in the ADCLK register (see Table 49 on page 64)
SCH2
SCH1
SCH0
Selected Analog input
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
1
1
1
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