参数资料
型号: AT83EB5114XXXTGRIL
厂商: ATMEL CORP
元件分类: 微控制器/微处理器
英文描述: Low-pin-count 8-bit microcontroller with A/D converter
中文描述: 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDSO20
封装: SO-20
文件页数: 86/95页
文件大小: 1126K
代理商: AT83EB5114XXXTGRIL
86
4311A–8051–01/05
Notes:
1. I
CC
under reset is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns (see Figure 42.), V
IL
=
V
SS
+ 0.5 V,
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; Vpp = RST = V
CC
. I
CC
would be slightly higher if a crystal oscillator used
2. Idle I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns, V
IL
= V
SS
+ 0.5 V, V
IH
= V
CC
-
0.5 V; XTAL2 N.C; Vpp = RST = V
SS
(see Figure 40.).
3. Power Down I
CC
is measured with all output pins disconnected; Vpp = V
SS
; XTAL2 NC.; RST = V
cc
(see Figure 41.).
4. Not Applicable
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
3.3V.
6. If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. When port configuration have weak pull-up activated.
9. When port configuration is quasi-bidirectional.
10. Operating I
CC
is measured with all output pins disconnected; XTAL1 driven with T
CLCH
, T
CHCL
= 5 ns (see Figure 42.), V
IL
=
V
SS
+ 0.5 V,
V
IH
= V
CC
- 0.5V; XTAL2 N.C.; RST= V
CC
;. The internal ROM runs the code 80 FE (label: SJMP label). I
CC
would be slightly
higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case.
Figure 38.
I
CC
Test Condition, under reset
Figure 39.
Operating I
CC
Test Condition
t
R
Supply rise time
1us
1s
Table 1.
DC Parameters for Low Voltage (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
V
CC
I
CC
V
CC
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
I
CC
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
RST
XTAL2
XTAL1
V
SS
V
CC
Reset = Vss after a high pulse
during at least 24 clock cycles
V
CC
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