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参数资料
| 型号： | AT84XAD001BTD |
| 厂商： | ATMEL CORP |
| 元件分类： | ADC |
| 英文描述： | Dual 8-bit 1 Gsps ADC |
| 中文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封装： | 20 X 20 MM, 1.4 MM HEIGHT, LQFP-144 |
| 文件页数： | 40/60页 |
| 文件大小： | 1343K |
| 代理商： | AT84XAD001BTD |
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40
AT84AD001B
2153C–BDC–04/04
Notes:
1. D9 must be set to “0”
2. Mode standby channel I: use analog input I Vini, Vinib and Clocki.
3. Mode standby channel Q: use analog input Q Vinq, Vinqb and Clockq.
4. Keep last calibration calculated value - no calibration phase: D11 = 0 and D10 = 1. No new calibration is required. The val-
ues taken into account for the gain and offset are either from the last calibration phase or are default values (reset values).
5. No calibration phase - no calibration value: D11 = 0 and D10 = 0. No new calibration phase is required. The gain and offset
compensation functions can be accessed externally by writing in the registers at address 010 for the offset compensation
and at address 011 for the gain compensation.
6. The control wait bit gives the possibility to change the internal setting for the auto-calibration phase:
For high clock rates (> 500 Msps) use a = b = 1.
For clock rates > 250 Msps and < 500 Msps use a = 1 and b = 0.
For clock rates > 125 Msps and < 250 Msps use a = 0 and b = 1.
For low clock rates < 125 Msps use a = 0 and b = 0.
3-wire Serial Interface Timing
Description
The 3-wire serial interface is a synchronous write-only serial interface made of three
wires:
sclk: serial clock input
sldn: serial load enable input
sdata: serial data input
The 3-wire serial interface gives write-only access to as many as 8 different internal reg-
isters of up to 16 bits each. The input format is always fixed with 3 bits of register
address followed by 16 bits of data. The data and address are entered with the Most
Significant Bit (MSB) first.
The write procedure is fully synchronous with the rising clock edge of “sclk” and
described in the write chronogram (Figure 44 on page 41).
“sldn” and “sdata” are sampled on each rising clock edge of “sclk” (clock cycle).
“sldn” must be set to 1 when no write procedure is performed.
A minimum of one rising clock edge (clock cycle) with “sldn” at 1 is required for a
correct start of the write procedure.
A write starts on the first clock cycle with “sldn” at 0. “sldn” must stay at 0 during the
complete write procedure.
During the first 3 clock cycles with “sldn” at 0, 3 bits of the register address from
MSB (a[2]) to LSB (a[0]) are entered.
During the next 16 clock cycles with “sldn” at 0, 16 bits of data from MSB (d[15]) to
LSB (d[0]) are entered.
An additional clock cycle with “sldn” at 0 is required for parallel transfer of the serial
data d[15:0] into the addressed register with address a[2:0]. This yields 20 clock
cycles with “sldn” at 0 for a normal write procedure.
Control wait bit
calibration
(6)
X
X
a
b
X
X
0
X
X
X
X
X
X
X
X
X
In 1:2 DMUX
FDataReady
I & Q = Fs/2
X
0
X
X
X
X
0
X
X
X
X
X
X
X
X
X
In 1:2 DMUX
FDataReady
I & Q = Fs/4
X
1
X
X
X
X
0
X
X
X
X
X
X
X
X
X
Table 13.
3-wire Serial Interface Data Setting Description (Continued)
Setting for Address:
000
D15
D14
D13
D12
D11
D10
D9
(1)
D8
D7
D6
D5
D4
D3
D2
D1
D0
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