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参数资料
| 型号： | AT84XAD001BTD |
| 厂商： | ATMEL CORP |
| 元件分类： | ADC |
| 英文描述： | Dual 8-bit 1 Gsps ADC |
| 中文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封装： | 20 X 20 MM, 1.4 MM HEIGHT, LQFP-144 |
| 文件页数： | 41/60页 |
| 文件大小： | 1343K |
| 代理商： | AT84XAD001BTD |
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41
AT84AD001B
2153C–BDC–04/04
A minimum of one clock cycle with “sldn” returned at 1 is requested to close the
write procedure and make the interface ready for a new write procedure. Any clock
cycle where “sldn” is at 1
before
the write procedure is completed interrupts this
procedure and no further data transfer to the internal registers is performed.
Additional clock cycles with “sldn” at 0
after
the parallel data transfer to the register
(done at the 20th consecutive clock cycle with “sldn” at 0) do not affect the write
procedure and are ignored.
It is possible to have only one clock cycle with “sldn” at 1 between two following write
procedures.
16 bits of data must always be entered even if the internal addressed register has
less than 16 bits. Unused bits (usually MSBs) are ignored. Bit signification and bit
positions for the internal registers are detailed in Table 12 on page 37.
To reset the registers, the Pin mode can be used as a reset pin for chip initialization,
even when the 3-wire serial interface is used.
Figure 44.
Write Chronogram
Figure 45.
Timing Definition
Reset
Write procedure
a[2]
a[1]
a[0]
d[15]
d[8]
d[7]
d[6]
d[5]
d[4]
d[3]
d[2]
d[1]
d[0]
1
2
3
4
5
13
14
15
16
17
18
19
20
Reset setting
Mode
sclk
sldn
sdata
Internal register
value
New d
Mode
sclk
sldn
sdata
Twlmode
Tdmode
Tssldn
Tssdata
Thsldn
Thsdata
Tdmode
Twsclk
Tsclk
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