参数资料
型号: AT86RF212-ZU
厂商: Atmel
文件页数: 132/172页
文件大小: 0K
描述: IC TXRX ZIGBE/802.15.4/ISM 32QFN
产品培训模块: MCU Wireless Solutions Product Line Introduction
标准包装: 2,450
频率: 700MHz,800MHz,900MHz
数据传输率 - 最大: 250kbps
调制或协议: 802.15.4 Zigbee,6LoWPAN,ISM
应用: ISM,ZigBee?
功率 - 输出: 10dBm
灵敏度: -110dBm
电源电压: 1.8 V ~ 3.6 V
电流 - 接收: 9.2mA
电流 - 传输: 25mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 托盘

9 Extended Feature Set
9.1 Security Module (AES)
The security module (AES) is characterized by:
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?
?
?
Hardware accelerated encryption and decryption
Compatible with AES-128 standard (128 bit key and data block size)
Support of ECB (encryption/decryption) mode and CBC (encryption) mode
Stand-alone operation, independent of other blocks
9.1.1 Overview
The security module is based on an AES-128 core according to FIPS197 standard,
refer to [9]. The security module is independent from other building blocks of the
AT86RF212. Encryption and decryption can be performed in parallel to a frame
transmission or reception.
Controlling of the security block is implemented as an SRAM access to address space
0x82 to 0x94. A Fast SRAM access mode allows simultaneously writing new data and
reading data from previously processed data within the same SPI transfer. This access
procedure is used to reduce the turnaround time for ECB mode, see section 9.1.5.
In addition, the security module contains another 128-bit register to store the initial key
used for security operations. This initial key is not modified by the security module.
9.1.2 Security Module Preparation
The use of the security module requires a configuration of the security engine before
starting a security operation. The required steps are listed in Table 9-1.
Table 9-1. AES Engine Configuration Steps
Step
1
2
Action
Key Setup
AES mode
Description
Write encryption or decryption key to SRAM
Select AES mode: ECB or CBC
Section
9.1.3
9.1.4
Select encryption or decryption
3
4
5
Write Data
Start operation
Read Data
Write plaintext or cipher text to SRAM
Start AES operation
Read cipher text or plaintext from SRAM
9.1.5
9.1.5
Before starting any security operation, a key must be written to the security engine. The
key set up requires the configuration of the AES engine KEY mode using register bits
AES_MODE (SRAM address 0x83, AES_CTRL). The following step selects the AES
mode, either electronic code book (ECB) or cipher block chaining (CBC). These modes
are explained in more detail in section 9.1.4. Further, encryption or decryption must be
selected with register bit AES_DIR (SRAM address 0x83, AES_CTRL).
After this, the 128-bit plain text or cipher text data has to be provided to the AES
hardware engine. The data uses the SRAM address range 0x84 – 0x93.
An encryption or decryption is initiated with register bit AES_REQUEST = 1 (SRAM
address 0x83, i.e. AES_CTRL, or the mirrored version SRAM address 0x94, i.e.
AES_CTRL_MIRROR).
132
AT86RF212
8168C-MCU Wireless-02/10
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