参数资料
型号: AT86RF212-ZU
厂商: Atmel
文件页数: 16/172页
文件大小: 0K
描述: IC TXRX ZIGBE/802.15.4/ISM 32QFN
产品培训模块: MCU Wireless Solutions Product Line Introduction
标准包装: 2,450
频率: 700MHz,800MHz,900MHz
数据传输率 - 最大: 250kbps
调制或协议: 802.15.4 Zigbee,6LoWPAN,ISM
应用: ISM,ZigBee?
功率 - 输出: 10dBm
灵敏度: -110dBm
电源电压: 1.8 V ~ 3.6 V
电流 - 接收: 9.2mA
电流 - 传输: 25mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 托盘
Referring to Figure 4-2 and Figure 4-3, MOSI is sampled at the rising edge of the SCLK
signal and the output is set at the falling edge of SCLK. The signal must be stable
before and after the rising edge of SCLK as specified by t 3 and t 4 ; refer to section 10.4,
parameters 10.4.5 and 10.4.6.
This SPI operational mode is commonly known as “SPI mode 0”.
4.3 SPI Protocol
Each SPI sequence starts with transferring a command byte from the SPI master via
MOSI (see Table 4-2) with MSB first. This command byte defines the SPI access mode
and additional mode-dependent information.
Table 4-2. SPI Command Byte Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access Mode
Access Type
1
1
0
1
Register address [5:0]
Register address [5:0]
Register access
Read access
Write access
0
0
0
0
0
1
0
1
1
1
0
0
Reserved
Reserved
Reserved
Reserved
Frame Buffer access
SRAM access
Read access
Write access
Read access
Write access
Each SPI transfer returns bytes back to the SPI master on MISO. The content of the
first byte is the PHY_STATUS field, see section 4.4.
In Figure 4-4 to Figure 4-14 and the following sections, logic values stated with XX on
MOSI are ignored by the radio transceiver but need to have a valid logic level. Return
values on MISO stated as XX shall be ignored by the microcontroller.
The different access modes are described within the following sections.
4.3.1 Register Access Mode
A register access mode is a two-byte read/write operation initiated by /SEL = L. The first
transferred byte on MOSI is the command byte, including an identifier bit (bit7 = 1), a
read/write select bit (bit 6), and a 6-bit register address.
On read access, the content of the selected register address is returned in the second
byte on MISO (see Figure 4-4).
Figure 4-4. Register Access Mode – Read Access
Note:
1. Each SPI access can be configured to return PHY status information
( PHY_STATUS ) on MISO, refer to section 4.4.
On write access, the second byte transferred on MOSI contains the write data to the
selected address (see Figure 4-5).
16
AT86RF212
8168C-MCU Wireless-02/10
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