参数资料
型号: AT86RF232-ZX
厂商: Atmel
文件页数: 56/175页
文件大小: 0K
描述: 2.4 GHZ ZIGBEE TRANSCEIVER
产品培训模块: AT86RF232 Low Power 2.4 GHz Wireless Transceiver
标准包装: 2,450
频率: 2.4GHz
数据传输率 - 最大: 250kbps
调制或协议: 802.15.4 Zigbee,6LoWPAN,ISM
应用: 通用
功率 - 输出: 3dBm
灵敏度: -100dBm
电源电压: 1.8 V ~ 3.6 V
电流 - 接收: 11.8mA
电流 - 传输: 13.8mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 托盘
acknowledgement frames not to be announced, which would otherwise always pass the
filter, regardless of whether they are intended for this device or not.
For backward compatibility to IEEE 802.15.4-2003 third level filter rule two (Frame
Version) can be disabled by register bits AACK_FVN_MODE (register 0x2E,
CSMA_SEED_1).
Frame filtering is available in Extended and Basic Operating Mode, refer to Section 7.1 ,
a frame passing the frame filtering generates an IRQ_5 (AMI), if enabled.
Notes:
1.
2.
Filter rule one is affected by register bits AACK_FLTR_RES_FT and
AACK_UPLD_RES_FT, Section 7.2.7 .
Filter rule two is affected by register bits AACK_FVN_MODE, Section 7.2.7 .
7.2.3.5 RX_AACK Slotted Operation – Slotted Acknowledgement
Atmel AT86RF232
supports slotted acknowledgement operation, refer
to
IEEE 802.15.4-2006, Section 7.5.6.4.2, in conjunction with the microcontroller.
In RX_AACK mode
with register bit SLOTTED_OPERATION (register 0x2C,
XAH_CTRL_0) set, the transmission of an acknowledgement frame has to be controlled
by the microcontroller. If an ACK frame has to be transmitted, the radio transceiver
expects a rising edge on pin 11 (SLP_TR) to actually start the transmission. This
waiting state is signaled two symbol periods after the reception of the last symbol of a
data or MAC command frame by register bits TRAC_STATUS (register 0x02,
XAH_CTRL_0), which are set to SUCCESS_WAIT_FOR_ACK in that case. In networks
using slotted operation the start of the acknowledgment frame, and thus the exact
timing, must be provided by the microcontroller.
A timing example of an RX_AACK transaction with register bit SLOTTED_OPERATION
(register 0x2C, XAH_CTRL_0) set is shown in Figure 7-12 . The acknowledgement
frame is ready to be transmitted two symbol times after the reception of the last symbol
of a data or MAC command frame. The transmission of the acknowledgement frame is
initiated by the microcontroller with the rising edge of pin 11 (SLP_TR) and starts
t TR10 = 16μs later. The interrupt latency t IRQ is specified in Section 12.4 .
Figure 7-12. Example Timing of an RX_AACK Transaction for Slotted Operation.
0
64
512
704
1026
time [ μ s]
Frame Type
TRX_STATE
RX_AACK_ON
SFD
Data Frame (Length = 10, ACK=1)
BUSY_RX_AACK
ACK Frame
RX_AACK_ON
RX/TX
IRQ
Typ. Processing Delay
RX
TRX_END
t IRQ
32 μ s
T X
ACK transmission initated by microcontroller
RX
(2 symbols)
SLP_TR
56
AT86RF232
waiting period signalled by register bits TRAC_STATUS
t TR10
SLP_TR
8321A – MCU Wireless – 10/11
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