参数资料
型号: AT89C51AC2-RLTUM
厂商: Atmel
文件页数: 33/121页
文件大小: 0K
描述: IC 8051 MCU FLASH 32K 44VQFP
产品培训模块: MCU Product Line Introduction
标准包装: 800
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 托盘
产品目录页面: 616 (CN2011-ZH PDF)
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
19
A/T89C51AC2
4127H–8051–02/08
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
Watchdog Reset
As detailed in Section “PCA Watchdog Timer”, page 80, the WDT generates a 96-clock
period pulse on the RST pin. In order to properly propagate this pulse to the rest of the
application in case of external capacitor or power-supply supervisor circuit, a 1K resis-
tor must be added as shown Figure 8.
Figure 8. Reset Circuitry for WDT reset out usage
Reset Recommendation
to Prevent Flash
Corruption
An example of bad initialization situation may occur in an instance where the bit
ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since
this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet
due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program
Counter is accidently in the range of the boot memory addresses then a flash access
(write or erase) may corrupt the Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage (power
supply failure, power supply switched off).
Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode,
program execution halts. Idle mode freezes the clock to the CPU at known states while
the peripherals continue to be clocked. The CPU status before entering Idle mode is
preserved, i.e., the program counter and program status word register retain their data
for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The
status of the Port pins during Idle mode is detailed in Table 14.
Entering Idle Mode
To enter Idle mode, you must set the IDL bit in PCON register (see Table 15). The
T89C51CC02 enters Idle mode upon execution of the instruction that sets IDL bit. The
instruction that sets IDL bit is the last instruction executed.
Note:
If IDL bit and PD bit are set simultaneously, the T89C51CC02 enters Power-down mode.
Then it does not go in Idle mode when exiting Power-down mode.
Exiting Idle Mode
There are two ways to exit Idle mode:
1.
Generate an enabled interrupt.
Hardware clears IDL bit in PCON register which restores the clock to the
CPU. Execution resumes with the interrupt service routine. Upon completion
of the interrupt service routine, program execution resumes with the
instruction immediately following the instruction that activated Idle mode.
R
S
T
RST
VSS
To CPU core
and peripherals
VDD
+
VSS
VDD
RST
1K
To other
on-board
circuitry
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