参数资料
型号: AT89C51AC2-RLTUM
厂商: Atmel
文件页数: 35/121页
文件大小: 0K
描述: IC 8051 MCU FLASH 32K 44VQFP
产品培训模块: MCU Product Line Introduction
标准包装: 800
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 托盘
产品目录页面: 616 (CN2011-ZH PDF)
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
20
A/T89C51AC2
4127H–8051–02/08
The general-purpose flags (GF1 and GF0 in PCON register) may be used to
indicate whether an interrupt occurred during normal operation or during Idle
mode. When Idle mode is exited by an interrupt, the interrupt service routine
may examine GF1 and GF0.
2.
Generate a reset.
A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution
momentarily resumes with the instruction immediately following the
instruction that activated the Idle mode and may continue for a number of
clock cycles before the internal reset algorithm takes control. Reset
initializes the T89C51CC02 and vectors the CPU to address C:0000h.
Notes:
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated Idle
mode should not write to a Port pin or to the external RAM.
2. If Idle mode is invoked by ADC Idle, the ADC conversion completion will exit Idle.
Power-down Mode
The Power-down mode places the T89C51CC02 in a very low power state. Power-down
mode stops the oscillator and freezes all clocks at known states. The CPU status prior to
entering Power-down mode is preserved, i.e., the program counter, program status
word register retain their data for the duration of Power-down mode. In addition, the
SFRs and RAM contents are preserved. The status of the Port pins during Power-down
mode is detailed in Table 14.
Entering Power-down Mode
To enter Power-down mode, set PD bit in PCON register. The T89C51CC02 enters the
Power-down mode upon execution of the instruction that sets PD bit. The instruction
that sets PD bit is the last instruction executed.
Exiting Power-down Mode
If VDD was reduced during the Power-down mode, do not exit Power-down mode until
VDD is restored to the normal operating level.
There are two ways to exit the Power-down mode:
1.
Generate an enabled external interrupt.
The T89C51CC02 provides capability to exit from Power-down using INT0#,
INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTx# input,
execution resumes when the input is released (see Figure 9) while using
KINx input, execution resumes after counting 1024 clock ensuring the
oscillator is restarted properly (see Figure 8). Execution resumes with the
interrupt service routine. Upon completion of the interrupt service routine,
program execution resumes with the instruction immediately following the
instruction that activated Power-down mode.
Note:
1. The external interrupt used to exit Power-down mode must be configured as level
sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,
the duration of the interrupt must be long enough to allow the oscillator to stabilize.
The execution will only resume when the interrupt is deasserted.
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
RAM content.
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