参数资料
型号: AT89C51ID2-SLRUM
厂商: Atmel
文件页数: 5/157页
文件大小: 0K
描述: IC 8051 MCU 64K FLASH 44-PLCC
产品培训模块: MCU Product Line Introduction
标准包装: 500
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 60MHz
连通性: I²C,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 标准包装
其它名称: AT89C51ID2-SLRUMDKR
102
AT89C51ID2
4289C–8051–11/05
Figure 39. Data Transmission Format (CPHA = 0)
Figure 40. Data Transmission Format (CPHA = 1)
Figure 41. CPHA/SS Timing
As shown in Figure 39, the first SCK edge is the MSB capture strobe. Therefore, the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each Byte transmitted (Figure 41).
Figure 40 shows an SPI transmission in which CPHA is ’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmis-
sions (Figure 41). This format may be preffered in systems having only one Master and
only one Slave driving the MISO data line.
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit6
bit5
bit4
bit3
bit2
bit1
MSB
LSB
13
24
5
6
7
8
Capture Point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Number
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit6
bit5
bit4
bit3
bit2
bit1
MSB
LSB
13
24
5
6
7
8
Capture Point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Number
Byte 1
Byte 2
Byte 3
MISO/MOSI
Master SS
Slave SS
(CPHA = 1)
Slave SS
(CPHA = 0)
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