参数资料
型号: AT89C51ID2-SLRUM
厂商: Atmel
文件页数: 8/157页
文件大小: 0K
描述: IC 8051 MCU 64K FLASH 44-PLCC
产品培训模块: MCU Product Line Introduction
标准包装: 500
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 60MHz
连通性: I²C,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
EEPROM 大小: 2K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 标准包装
其它名称: AT89C51ID2-SLRUMDKR
105
AT89C51ID2
4289C–8051–11/05
Reset Value = 0001 0100b
Not bit addressable
Serial Peripheral Status Register
(SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Table 80 describes the SPSTA register and explains the use of every bit in the register.
Table 80. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
1
SPR1
SPR2
SPR1
SPR0 Serial Peripheral Rate
00
0
F
CLK PERIPH /2
00
1
F
CLK PERIPH /4
01
0
F
CLK PERIPH /8
01
1
F
CLK PERIPH /16
10
0
F
CLK PERIPH /32
10
1
F
CLK PERIPH /64
11
0
F
CLK PERIPH /128
1
Invalid
0
SPR0
Bit Number
Bit Mnemonic
Description
Table 2.
76
543
210
SPIF
WCOL
SSERR
MODF
-
Bit
Number
Bit
Mnemonic Description
7SPIF
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
6WCOL
Write Collision Flag
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
5
SSERR
Synchronous Serial Slave Error Flag
Set by hardware when SS is deasserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
4MODF
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit
2-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
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