参数资料
型号: AT89C51RB2-SLRIL
厂商: Atmel
文件页数: 38/127页
文件大小: 0K
描述: IC MCU FLASH 8051 16K 3V 44-PLCC
标准包装: 1
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LCC(J 形引线)
包装: 剪切带 (CT)
配用: AT89STK-11-ND - KIT STARTER FOR AT89C51RX2
其它名称: AT89C51RB2SLRILCT
18
AT89C51RB2/RC2
4180E–8051–10/06
Table 15. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
Reset Value = 0000 000’HSB. X2’b (see Table 65 “Hardware Security Byte”)
Not bit addressable
76
54
32
1
0
-
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic
Description
7
Reserved
6WDX2
Watchdog Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5PCAX2
Programmable Counter Array Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
4SIX2
Enhanced UART Clock (Mode 0 and 2)
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
3T2X2
Timer 2 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2T1X2
Timer 1 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
1T0X2
Timer0 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
0X2
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU
and all the peripherals. Set to select 6 clock periods per machine cycle (X2
mode) and to enable the individual peripherals’X2’ bits. Programmed by
hardware after Power-up regarding Hardware Security Byte (HSB), Default
setting, X2 is cleared.
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