参数资料
型号: AT91SAM7X-EK
厂商: Atmel
文件页数: 8/44页
文件大小: 0K
描述: KIT EVAL FOR AT91SAM7X256/128
产品培训模块: AT91SAM7X and SAM7XC Flash-based Microcontrollers
MCU Product Line Introduction
标准包装: 1
系列: AT91SAM 智能 ARM
类型: MCU
适用于相关产品: AT91SAM7X256,AT91SAM7X128
所含物品: 板,线缆,DVD,电源
相关产品: AT91SAM7X256-CU-999-ND - IC MCU ARM7 256KB FLASH 100TFBGA
AT91SAM7X128-CU-999-ND - IC MCU ARM7 128KB FLASH 100TFBGA
AT91SAM7X128-AU-999-ND - IC MCU ARM7 128KB FLASH 100LQFP
AT91SAM7X512-CU-ND - MCU ARM 512K HS FLASH 100-TFBGA
AT91SAM7X512-AU-ND - MCU ARM 512K HS FLASH 100-LQFP
AT91SAM7X256-CU-ND - MCU ARM 256K HS FLASH 100-TFBGA
AT91SAM7X128-CU-ND - MCU ARM 128K HS FLASH 100-TFBGA
AT91SAM7X256-AU-999TR-ND - IC ARM7 MCU 256K FLASH 100-LQFP
AT91SAM7X256-AU-ND - IC ARM7 MCU FLASH 256K 100LQFP
AT91SAM7X128-AU-ND - IC ARM7 MCU FLASH 128K 100LQFP
16
6120GS–ATARM–07-Apr-11
SAM7X512/256/128 Summary
Embedded Flash Controller
– Embedded Flash interface, up to three programmable wait states
– Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required
wait states
– Key-protected program, erase and lock/unlock sequencer
– Single command for erasing, programming and locking operations
– Interrupt generation in case of forbidden operation
7.4
Peripheral DMA Controller
Handles data transfer between peripherals and memories
Thirteen channels
– Two for each USART
– Two for the Debug Unit
– Two for the Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for the Analog-to-digital Converter
Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
Next Pointer management for reducing interrupt latency requirements
Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):
Receive
DBGU
Receive
USART0
Receive
USART1
Receive
SSC
Receive
ADC
Receive
SPI0
Receive
SPI1
Transmit
DBGU
Transmit
USART0
Transmit
USART
Transmit
SSC
Transmit
SPI0
Transmit
SPI1
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