参数资料
| 型号： | AT91SAM9G20B-CFU |
| 厂商： | Atmel |
| 文件页数： | 13/42页 |
| 文件大小： | 0K |
| 描述： | IC MCU ARM9 247-LFBGA |
| 产品培训模块： | MCU Product Line Introduction |
| 标准包装： | 240 |
| 系列： | SAM9G |
| 核心处理器： | ARM9 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 400MHz |
| 连通性： | EBI/EMI，以太网，I²C，IrDA，ISI，MMC，SPI，SSC，UART/USART，USB |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 96 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | ROM |
| RAM 容量： | 96K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 0.9 V ~ 1.1 V |
| 数据转换器： | A/D 4x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 247-TFBGA |
| 包装： | 托盘 |
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20
6384DS–ATARM–13-Jan-10
AT91SAM9G20 Summary
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks 1 to
7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level
of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals
and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap. Refer to Table 8-1, “Internal Memory Mapping,” on page 20 for details.
A complete memory map is presented in Figure 8-1 on page 19.
8.1
Embedded Memories
64-KByte ROM
– Single Cycle Access at full matrix speed
Two 16-Kbyte Fast SRAM
– Single Cycle Access at full matrix speed
8.1.1
Boot Strategies
Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status and the BMS state at reset.
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted. When REMAP = 1, BMS is ignored. Refer to
the Bus Matrix Section for more details.
Table 8-1.
Internal Memory Mapping
Address
REMAP = 0
REMAP = 1
BMS = 1
BMS = 0
0x0000 0000
ROM
EBI_NCS0
SRAM0 16K
0x0010 0000
ROM
0x0020 0000
SRAM0 16K
0x0030 0000
SRAM1 16K
0x0050 0000
USB Host User Interface
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