参数资料
型号: AT91SAM9G20B-CFU
厂商: Atmel
文件页数: 7/42页
文件大小: 0K
描述: IC MCU ARM9 247-LFBGA
产品培训模块: MCU Product Line Introduction
标准包装: 240
系列: SAM9G
核心处理器: ARM9
芯体尺寸: 16/32-位
速度: 400MHz
连通性: EBI/EMI,以太网,I²C,IrDA,ISI,MMC,SPI,SSC,UART/USART,USB
外围设备: DMA,POR,PWM,WDT
输入/输出数: 96
程序存储器容量: 64KB(64K x 8)
程序存储器类型: ROM
RAM 容量: 96K x 8
电压 - 电源 (Vcc/Vdd): 0.9 V ~ 1.1 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 247-TFBGA
包装: 托盘
15
6384DS–ATARM–13-Jan-10
AT91SAM9G20 Summary
7.
Processor and Architecture
7.1
ARM926EJ-S Processor
RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
DSP Instruction Extensions
5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
32-Kbyte Data Cache, 32-Kbyte Instruction Cache
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
Write Buffer
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
Standard ARM v4 and v5 Memory Management Unit (MMU)
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
each quarter of the page
– 16 embedded domains
Bus Interface Unit (BIU)
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
system flexibility
– Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
7.2
Bus Matrix
6-layer Matrix, handling requests from 6 masters
Programmable Arbitration strategy
– Fixed-priority Arbitration
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