参数资料
型号: ATICE50POD
厂商: Atmel
文件页数: 27/73页
文件大小: 0K
描述: REPLACEMENT POD FOR ICE40,ICE50
标准包装: 1
附件类型: POD 替代套件
适用于相关产品: AVR ICE40 和 ICE50
产品目录页面: 615 (CN2011-ZH PDF)
General Description
Table 3-3. Data Direction
Delay
Typical Value (2V Target)
Typical Value (5V Target)
t OHL
t OLH
13 ns
13 ns
10 ns
10 ns
t IHL
13 ns
10 ns
t ILH(4)
13 ns
10 ns
Notes:
1.
2.
3.
4.
tOHL = Time from clearing the PORT register to the output changes
tOLH = Time from setting the PORT register to the output changes
tIHL = Time from changing the input level to the PIN signal changes (high to low)
tILH = Time from changing the input level to the PIN signal changes (low to high)
Figure 3-19 shows the timing data for tristating/driving the IO pins. Table 3-4 shows
related typical data.
Figure 3-19. Timing Data
DDRxy
PORTxy
t DZL
t DLZ
Pxy
t DZH
t DHZ
High Z
Table 3-4. Timing Data
High Z
High Z
Delay
Typical Value (2V target)
Typical Value (5V target)
t DZL
15 ns
15 ns
t DLZ(2)
15 ns
15 ns
t DZH
t DHZ
15 ns
15 ns
15 ns
15 ns
Notes:
1.
2.
3.
4.
tDZL = time from setting the DDR register to the output is driven low.
tDLZ = time from clearing the DDR register to the output is tristated.
tDZH = time from setting the DDR register to the output is driven high.
tDHZ = time from clearing the DDR register to the output is driven low.
The drive capability of the output buffers are ± 24 mA at 3V V CC . This slightly exceeds
the driving capability of the actual parts. The operating voltage range of the IO circuits
are 2 V CC to 5.5 V CC . At 2V V CC the buffers are able to sink 25 mA with a maximal output
low voltage (VOLmax) of 1V.
The hysteresis voltage for the input buffers are typically 0.8V at 3V V CC and 1.2V at 5.5V
V CC .
ICE50 User Guide
3-13
2523A–AVR–11/02
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