参数资料
| 型号： | ATICE50POD |
| 厂商： | Atmel |
| 文件页数： | 57/73页 |
| 文件大小： | 0K |
| 描述： | REPLACEMENT POD FOR ICE40,ICE50 |
| 标准包装： | 1 |
| 附件类型： | POD 替代套件 |
| 适用于相关产品： | AVR ICE40 和 ICE50 |
| 产品目录页面： | 615 (CN2011-ZH PDF) |
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Trace
of the Program Counter, i.e., it is the address in the Program Memory of the
instruction currently being executed. For multicycle instructions, the contents of this
column may contain other values. See the description of the various instruction.
Valid Instruction (VI): This is a status flag which tells if the instruction is fetched and
ready for execution. For multicycle instructions this bit will only be “1” in the first cycle.
Instruction Column (Ins): This column contains the instruction word and the
disassembled mnemonic representation of all instructions being executed. For
multicycle instructions, this column will only contain information in the first cycle of the
instruction. For the remaining cycles of the instructions, the column is left blank.
Data Address Column (Dat.Addr): This column contains the active address in the data
memory space, and only contains information during some cycles in instructions
reading from or writing to the data memory. See the description of the instructions to
see what this field means for each instruction.
Register File Low/High Value column (RL &RH): For some of the instructions, the
result being fed back to the Register File is also sent to the Trace Buffer. For other
instructions, this field does not contain any information. See the description of the
instructions to see what this means in the various cases.
Register File Valid Signal (VR): This status bit indicates if the values on column RL
and RH is valid in this cycle..
Spare Signals (S): For future use.
Status Register Column (SR): Contains the AVR Status Register.
Function ID (PS): This column contains the Function ID number.
Interrupt Acknowledge Column: If an interrupt routine is invoked this column will
contain a “1” else a “0”.
ICE50 User Guide
7-3
2523A–AVR–11/02
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