参数资料
型号: ATMEGA1284P-MUR
厂商: Atmel
文件页数: 43/160页
文件大小: 0K
描述: MCU AVR 128KB FLASH 20MHZ 44VQFN
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 4,000
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 128KB(64K x 16)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VFQFN 裸露焊盘
包装: 带卷 (TR)
配用: ATSTK600-ND - DEV KIT FOR AVR/AVR32
其它名称: ATMEGA1284P-MUR-ND
137
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB bits are always read as zero.
16.12.4
TCNT1H and TCNT1L –Timer/Counter1
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-
pare match between TCNT1 and one of the OCRnx Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
16.12.5
TCNT3H and TCNT3L –Timer/Counter3
The two Timer/Counter I/O locations (TCNT3H and TCNT3L, combined TCNT3) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
Modifying the counter (TCNT3) while the counter is running introduces a risk of missing a com-
pare match between TCNT3 and one of the OCRnx Registers.
Writing to the TCNT3 Register blocks (removes) the compare match on the following timer clock
for all compare units.
16.12.6
OCR1AH and OCR1AL – Output Compare Register1 A
Bit
76543210
TCNT1[15:8]
TCNT1H
TCNT1[7:0]
TCNT1L
Read/Write
R/W
Initial Value
00000000
Bit
76543210
(0x95)
TCNT3[15:8]
TCNT3H
(0x94)
TCNT3[7:0]
TCNT3L
Read/Write
R/W
Initial Value
00000000
Bit
76543210
OCR1A[15:8]
OCR1AH
OCR1A[7:0]
OCR1AL
Read/Write
R/W
Initial Value
00000000
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