参数资料
型号: ATMEGA1284P-MUR
厂商: Atmel
文件页数: 86/160页
文件大小: 0K
描述: MCU AVR 128KB FLASH 20MHZ 44VQFN
产品培训模块: MCU Product Line Introduction
megaAVR Introduction
标准包装: 4,000
系列: AVR® ATmega
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 128KB(64K x 16)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VFQFN 裸露焊盘
包装: 带卷 (TR)
配用: ATSTK600-ND - DEV KIT FOR AVR/AVR32
其它名称: ATMEGA1284P-MUR-ND
31
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
9.1.3
Flash Clock – clk
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
9.1.4
Asynchronous Timer Clock – clk
ASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows
using this Timer/Counter as a real-time counter even when the device is in sleep mode.
9.1.5
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
9.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Note:
1. For all fuses “1” means unprogrammed while “0” means programmed.
9.2.1
Default Clock Source
The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro-
grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out
period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that
all users can make their desired clock source setting using any available programming interface.
9.2.2
Clock Startup Sequence
Any clock source needs a sufficient V
CC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient V
CC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. ”On-chip Debug System” on page 46
describes the start conditions for the internal reset. The delay (t
TOUT) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
Table 9-1.
Device clocking options select (1).
Device Clocking Option
CKSEL3..0
Low Power Crystal Oscillator
1111 - 1000
Full Swing Crystal Oscillator
0111 - 0110
Low Frequency Crystal Oscillator
0101 - 0100
Internal 128kHz RC Oscillator
0011
Calibrated Internal RC Oscillator
0010
External Clock
0000
Reserved
0001
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